Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

Abstract: The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

Abstract: A disk drive that has a plurality of heads coupled to one or more disks. The heads have air bearing surfaces that compensate for a radial crown and a radial camber of an adjacent disk to maintain a flying height at a relatively constant level across the disk surface. By way of example, the air bearing surfaces may have crown and camber sensitivities that are opposite in sign from the crown and camber sensitivities created by the disk. The opposite sensitivities offset the sensitivities of the disk to maintain an essentially constant flying height as the head moves across the surface of a disk.

Abstract: Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

Abstract: An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

Abstract: The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.

Abstract: A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a portion of the doped deposition, deposition of an undoped insulator in the trench and removal of a portion of the doped and undoped insulators.

Abstract: A method and apparatus for detecting a defective disk for a hard disk drive. The method includes placing a disk into a tester so that a first side of the disk is adjacent to a first head of the tester and a second side of the disk is adjacent to a second head. First data is read from the first side of the disk, and second data is read from the second side of the disk. The disk is then flipped so that the second side is adjacent to the first head and the first side is adjacent to the second head. Third data is read from the first side. Fourth data is read from the second side. A first area between a curve generated from the first data and a curve generated from the third data is calculated. Likewise, a second area is calculated between a curve generated from the second data and a curve generated from the fourth data. An average of the first and second areas is then calculated and used to detect a defective disk.

Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

Abstract: A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.

Abstract: Thermal pole tip protrusion is caused by the materials in and around the head slider expanding during write operations till part of those materials protrude, leading to contact with the rotating disk surface, altering the flying height and often wearing down part of the disk surface. While it is well known that read-write heads expand during writing, the inventors are unaware of anyone else who recognized this situation's significance, particularly as the flying height decreases and the data rates increase, both of which are required for high areal density disk drives. The inventors realized that they could detect the problem at the spin stand level by testing head gimbal assemblies to reliably, and inexpensively, predict the tendency for thermal pole tip protrusion. This leads to selection of head gimbal assemblies, which do not have the thermal pole tip protrusion tendency.

Abstract: A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate over-drive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.

Abstract: A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate overdrive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.

Abstract: Thermal pole tip protrusion is caused by materials in and around head slider expanding during write operations till they protrude, leading to contact with the rotating disk surface, altering the flying height and often wearing down part of the disk surface. While well known that read-write heads expand during writing, the inventors who recognized this situation's significance, particularly as flying height decreases and data rates increase, both required for high areal density disk drives. The inventors realized that they could detect the problem at the spin stand level by testing head gimbal assemblies to reliably, and inexpensively, predict the tendency for thermal pole tip protrusion. This leads to selection of head gimbal assemblies, which do not have the thermal pole tip protrusion tendency. The selected head gimbal assemblies have better reliability, as do actuators and disk drives made with the selected head gimbal assemblies.

Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

Abstract: A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a pair of deep trenches formed within a semiconductor substrate. The pair of deep trenches has a dielectric material formed on side and bottom surfaces thereof, and includes a conductive fill material therein. Bottom portions of the pair of deep trenches are merged with one another so as to provide an electrically conductive path therethrough.

Abstract: Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substantially arbitrary low voltage in accordance with control signals applied to the gate of the transistor to cause the transistor to exhibit a variable threshold which maintains good performance at low supply voltages and reduces power consumption/dissipation which is particularly advantageous in portable electronic devices. Floating body effects (when the transistor substrate in disconnected from a voltage source in the “on” state) are avoided since the substrate is discharged when the transistor is switched to the “off” state. The transistor configuration can be employed with both n-type and p-type transistors which may be in complementary pairs.

Abstract: A disk drive that has a plurality of heads coupled to one or more disks. The heads have air bearing surfaces that compensate for a radial crown and a radial camber of an adjacent disk to maintain a flying height at a relatively constant level across the disk surface. By way of example, the air bearing surfaces may have crown and camber sensitivities that are opposite in sign from the crown and camber sensitivities created by the disk. The opposite sensitivities offset the sensitivities of the disk to maintain an essentially constant flying height as the head moves across the surface of a disk.

Abstract: Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

Abstract: A structure for use as a MOSFET employs an SOI wafer with a SiGe island resting on the SOI layer and extending between two blocks that serve as source and drain; epitaxially grown Si on the vertical surfaces of the SiGe forms the transistor channel. The lattice structure of the SiGe is arranged such that the epitaxial Si has little or no strain in the direction between the S and D and a significant strain perpendicular to that direction.