Patents by Inventor Georg Tempel

Georg Tempel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110159661
    Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Inventors: Laurent Breuil, Franz Schuler, Georg Tempel
  • Patent number: 7923342
    Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: April 12, 2011
    Assignee: Infineon Technologies AG
    Inventors: Laurent Breuil, Franz Schuler, Georg Tempel
  • Publication number: 20110003457
    Abstract: The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (10, 11), a side wall insulation layer (6) and an electrically conductive filling layer (7), which is electrically connected to a predetermined doping region (1) of the semiconductor substrate in a bottom region of the trench. The use of a trench contact (DTC), which has a deep contact trench with a side wall insulation layer (6) and an electrically conductive filling layer (7), which is likewise electrically connected to the predetermined doping region (1) of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 6, 2011
    Inventors: Franz Schuler, Georg Tempel
  • Patent number: 7847325
    Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: December 7, 2010
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Poeppel, Georg Tempel
  • Publication number: 20100129972
    Abstract: A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.
    Type: Application
    Filed: January 28, 2010
    Publication date: May 27, 2010
    Inventors: Ronald Kakoschke, Franz Schuler, Georg Tempel
  • Patent number: 7709836
    Abstract: The invention relates to a detector arrangement (100), a method for the detection of electrical charge carriers and use of an ONO field effect transistor for detection of an electrical charge. The detector arrangement (100) has an ONO field effect transistor embodied on and/or in a substrate (101), for the detection of electrical charge carriers, such that the electrical charge carrier (103) for detection may be introduced into die ONO field effect transistor layer sequence (102), a recording unit (104), coupled to the ONO field effect transistor, for recording an electrical signal characteristic of the amount and/or the charge carrier type for the electrical charge carrier (103) introduced into the ONO layer sequence (102) and an analytical unit for determining the amount and/or the charge carrier type of the electrical charge carrier (103) introduced into the ONO layer sequence (102) from the characteristic electrical signal.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: May 4, 2010
    Assignee: Infineon Technologies AG
    Inventors: Bernhard Knott, Georg Tempel
  • Patent number: 7709884
    Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: May 4, 2010
    Assignee: Infineon Technologies AG
    Inventors: Franz Schuler, Georg Tempel
  • Publication number: 20100084691
    Abstract: The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.
    Type: Application
    Filed: October 27, 2009
    Publication date: April 8, 2010
    Applicant: Infineon Technologies AG
    Inventor: Georg Tempel
  • Patent number: 7687842
    Abstract: A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: March 30, 2010
    Assignee: Infineon Technologies AG
    Inventors: Ronald Kakoschke, Franz Schuler, Georg Tempel
  • Publication number: 20100006925
    Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.
    Type: Application
    Filed: September 17, 2009
    Publication date: January 14, 2010
    Applicant: Infineon Technologies AG
    Inventors: Franz Schuler, Georg Tempel
  • Patent number: 7642544
    Abstract: The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: January 5, 2010
    Assignee: Infineon Technologies AG
    Inventor: Georg Tempel
  • Publication number: 20090176358
    Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.
    Type: Application
    Filed: March 12, 2009
    Publication date: July 9, 2009
    Inventors: Gerhard Poeppel, Georg Tempel
  • Patent number: 7541637
    Abstract: The invention relates to a nonvolatile semiconductor storage element and an associated production and control method, the storage element includes a semiconductor substrate having a source region, a drain region and an intermediate channel region. On a first portion of the channel region, a control layer is formed and insulated from the channel region by a first insulating layer whereas respective charge storage layers are formed in a second portion of the channel region and are insulated from the channel region by a second insulating layer. On the charge storage layer, a programming layer is formed and insulated from the charge storage layer by a third insulating layer and is electrically connected to a respective source region and drain region via a respective interconnect layer.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: June 2, 2009
    Assignee: Infineon Technologies AG
    Inventors: Franz Schuler, Georg Tempel
  • Patent number: 7528038
    Abstract: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: May 5, 2009
    Assignee: Infineon Technologies AG
    Inventors: Franz Schuler, Georg Tempel
  • Publication number: 20090020800
    Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.
    Type: Application
    Filed: July 18, 2007
    Publication date: January 22, 2009
    Inventors: Georg Tempel, Ernst-Otto Andersen, Achim Gratz
  • Publication number: 20080296662
    Abstract: A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 4, 2008
    Inventors: Gerhard Poeppel, Georg Tempel
  • Patent number: 7442756
    Abstract: A compound and method for sealing or protecting porous materials used in semiconductor fabrication, and in particular for protecting the inner walls of trenches or recesses or vias which are present in such materials. Specifically, compounds and the method of use of the compounds in which polymer compounds comprising functional groups A and B are used to seal surface-exposed pores in porous materials used in chip production.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: October 28, 2008
    Assignee: Infineon Technologies AG
    Inventors: Ludger Heiliger, Michael Schmidt, Georg Tempel
  • Publication number: 20080206931
    Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.
    Type: Application
    Filed: February 29, 2008
    Publication date: August 28, 2008
    Inventors: Laurent Breuil, Franz Schuler, Georg Tempel
  • Publication number: 20080173926
    Abstract: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.
    Type: Application
    Filed: March 24, 2008
    Publication date: July 24, 2008
    Inventors: Franz Schuler, Georg Tempel
  • Patent number: 7399673
    Abstract: In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the word lines into each a first diffusion region adjacent to a first trench of a first charge-trapping memory cell and a second diffusion region adjacent to a first trench of a second charge-trapping memory cell. The depth of the further trench is sufficient to impede hot charge carrier exchange between neighboring memory cells. For this purpose the further trenches are filled with dielectric material, e.g., an oxide. The depth of the further trenches may be, e.g., half of that of the word line trench, and the width may, e.g., amount to 15-20 nm.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: July 15, 2008
    Assignee: Infineon Technologies AG
    Inventor: Georg Tempel