Abstract: A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

Abstract: A memory circuit arrangement includes a switching element per column that can be used to connect or disconnect two bit lines for memory cells of a column. The switching element leads to a reduction of the chip area and/or to an improvement in the electronic properties of the memory circuit arrangement.

Abstract: One aspect of the invention relates to a non-volatile memory cell array and a fabrication method thereof. The non-volatile memory cell array includes first wordlines running in parallel along a first direction as well as second wordlines running in parallel along a second direction. Said first wordlines provide gate electrodes of a first part of non-volatile memory cells arranged along said second direction, whereas said second wordlines provide gate electrodes of a second part of non-volatile memory cells arranged along said first direction.

Abstract: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

Abstract: The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

Abstract: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

Abstract: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

Abstract: In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the word lines into each a first diffusion region adjacent to a first trench of a first charge-trapping memory cell and a second diffusion region adjacent to a first trench of a second charge-trapping memory cell. The depth of the further trench is sufficient to impede hot charge carrier exchange between neighboring memory cells. For this purpose the further trenches are filled with dielectric material, e.g., an oxide. The depth of the further trenches may be, e.g., half of that of the word line trench, and the width may, e.g., amount to 15-20 nm.

Abstract: The invention relates to a detector arrangement (100), a method for the detection of electrical charge carriers and use of an ONO field effect transistor for detection of an electrical charge. The detector arrangement (100) has an ONO field effect transistor embodied on and/or in a substrate (101), for the detection of electrical charge carriers, such that the electrical charge carrier (103) for detection may be introduced into die ONO field effect transistor layer sequence (102), a recording unit (104), coupled to the ONO field effect transistor, for recording an electrical signal characteristic of the amount and/or the charge carrier type for the electrical charge carrier (103) introduced into the ONO layer sequence (102) and an analytical unit for determining the amount and/or the charge carrier type of the electrical charge carrier (103) introduced into the ONO layer sequence (102) from the characteristic electrical signal.

Abstract: The invention relates to a process for sealing plasma-damaged, porous low-k materials on Si substrates, in which self-aligning molecules (SAMs) are applied to the low-k material, and then a diffusion barrier is applied to the low-k material. The invention is based on the object of providing a process for sealing plasma-damaged, porous low-k materials on Si substrates, which allows an improved distribution of the SAMs to be achieved, in particular in the case of structures with a high aspect ratio, and which allows the low-k materials to be repaired, dewatered and sealed. According to the invention, this is achieved by virtue of the fact that the deposition of the SAMs is carried out using a supercritical CO2 process (scCO2 process), by the wafers being introduced into a process chamber, that CO2 and SAMs are introduced into the process chamber and the process chamber is pressurized, that the wafers are heated to a temperature of over 35° C. up to 300° C.

Abstract: The invention relates to a nonvolatile semiconductor storage element and an associated production and control method, comprising a semiconductor substrate (1) in which a source region (S), a drain region (D) and an intermediate channel region are formed. On a first part section (I) of the channel region, a control layer (5) is formed and insulated from the channel region by a first insulating layer (2A) whereas respective charge storage layers (3A and 3B) are formed in a second part section (IIA, IIB) of the channel region and are insulated from the channel region by a second insulating layer (2BA and 2BB). On the charge storage layer (3A, 3B), a programming layer (6A, 6B) is formed and insulated from that by a third insulating layer (4A, 4B) and is electrically connected to a respective source region (S) and drain region (D) via a respective interconnect layer (6AA, 6BB).

Abstract: Prior to the reprogramming of a selected flash memory cell of a memory cell array, electrons being removed from the memory layer (M) in the channel region (C) by Fowler-Nordheim tunneling, a lower potential for incipient programming of the memory cell is applied to the relevant word line (WLn) while the associated bit line (BLm) remains at the basic potential. What is thereby achieved is that a gate disturb occurring during the programming operation does not lead to erratic bits along the affected word line (WLn).

Abstract: The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

Abstract: In the course of a method for fabricating a field-effect transistor having a floating gate, a structure is formed which has uncovered sidewalls of a layer made of the material for forming the floating gate and which is exposed to an oxidizing atmosphere in order to coat the sidewalls. At the same time, other regions of the structure have an insulating oxide layer. At a point in time prior to the action of an oxidizing atmosphere, nitrogen is implanted into the material of the floating gate in a quantity that appreciably reduces the oxidation at the sidewalls thereof.

Abstract: The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

Abstract: The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (10, 11), a side wall insulation layer (6) and an electrically conductive filling layer (7), which is electrically connected to a predetermined doping region (1) of the semiconductor substrate in a bottom region of the trench. The use of a trench contact (DTC), which has a deep contact trench with a side wall insulation layer (6) and an electrically conductive filling layer (7), which is likewise electrically connected to the predetermined doping region (1) of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.

Abstract: A nonvolatile memory element and to associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.