Abstract: The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.

Abstract: A memory circuit arrangement includes a switching element per column that can be used to connect or disconnect two bit lines for memory cells of a column. The switching element leads to a reduction of the chip area and/or to an improvement in the electronic properties of the memory circuit arrangement.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

Abstract: A compound and method for sealing or protecting porous materials used in semiconductor fabrication, and in particular for protecting the inner walls of trenches or recesses or vias which are present in such materials. Specifically, compounds and the method of use of the compounds in which polymer compounds comprising functional groups A and B are used to seal surface-exposed pores in porous materials used in chip production.

Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

Abstract: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: Prior to the reprogramming of a selected flash memory cell of a memory cell array, electrons being removed from the memory layer (M) in the channel region (C) by Fowler-Nordheim tunneling, a lower potential for incipient programming of the memory cell is applied to the relevant word line (WLn) while the associated bit line (BLm) remains at the basic potential. What is thereby achieved is that a gate disturb occurring during the programming operation does not lead to erratic bits along the affected word line (WLn).

Abstract: The invention relates to a process for sealing plasma-damaged, porous low-k materials on Si substrates, in which self-aligning molecules (SAMs) are applied to the low-k material, and then a diffusion barrier is applied to the low-k material. The invention is based on the object of providing a process for sealing plasma-damaged, porous low-k materials on Si substrates, which allows an improved distribution of the SAMs to be achieved, in particular in the case of structures with a high aspect ratio, and which allows the low-k materials to be repaired, dewatered and sealed. According to the invention, this is achieved by virtue of the fact that the deposition of the SAMs is carried out using a supercritical CO2 process (scCO2 process), by the wafers being introduced into a process chamber, that CO2 and SAMs are introduced into the process chamber and the process chamber is pressurized, that the wafers are heated to a temperature of over 35° C. up to 300° C.

Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

Abstract: The invention relates to a semiconductor circuit configuration and to an associated fabrication method, in which a semiconductor substrate has a plurality of word lines and a plurality of bit lines for the row by row and column by column driving of a matrix of switching elements. In this case, a plurality of electrically conductive connection strips for connecting source and drain regions in the active region to the respective bit lines are formed between the word lines such that they directly make contact with the source and drain regions at the surface of the semiconductor substrate in the active region. In this way, a particularly compact cell area is obtained in conjunction with very simple lithographic conditions.

Abstract: A nonvolatile semiconductor memory cell, an associated semiconductor circuit configuration and also a fabrication method, in which, in a substrate, active regions are formed with a first insulating layer situated above them, a charge-storing layer, a second insulating layer and a control layer. In order to realize a particularly small cell area, in a third insulating layer situated thereabove, openings are formed above at least partial regions of source/drain regions, which are each directly contact-connected via the openings by source and drain lines formed on an insulating web.

Abstract: Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates are set at a voltage of the same polarity as the programming voltage and at a magnitude of about half the programming voltage. The source is allowed to float and the drain (bitline) and body are set at a low level and at a polarity opposite to the programming voltage polarity.

Abstract: A nonvolatile semiconductor memory cell, an associated semiconductor circuit configuration and also a fabrication method, in which, in a substrate, active regions are formed with a first insulating layer situated above them, a charge-storing layer, a second insulating layer and a control layer. In order to realize a particularly small cell area, in a third insulating layer situated thereabove, openings are formed above at least partial regions of source/drain regions, which are each directly contact-connected via the openings by source and drain lines formed on an insulating web.

Abstract: The invention relates to a semiconductor circuit configuration and to an associated fabrication method, in which a semiconductor substrate has a plurality of word lines and a plurality of bit lines for the row by row and column by column driving of a matrix of switching elements. In this case, a plurality of electrically conductive connection strips for connecting source and drain regions in the active region to the respective bit lines are formed between the word lines such that they directly make contact with the source and drain regions at the surface of the semiconductor substrate in the active region. In this way, a particularly compact cell area is obtained in conjunction with very simple lithographic conditions.

Abstract: Flash EEPROM cells are erased and recovered to a common threshold voltage by a two step process. First, the cells are erased. Second, the fixed (control) gates are set at a voltage of the same polarity as the programming voltage and at a magnitude of about half the programming voltage. The source is allowed to float and the drain (bitline) and body are set at a low level and at a polarity opposite to the programming voltage polarity.

Abstract: A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.

Abstract: A method of flash memory cell programming is provided which uses a uniform electric potential across tunnel oxide. The tight Vt distribution and very stable Vt shift over program/erase cycling allows for a multi-level cell capable of having more than 2 bits per cell.