Abstract: A sense amplifier driver activates a plurality of sense amplifiers coupled to respective digit lines in each of a plurality of memory-cell arrays. The sense amplifiers each have first and second activation nodes. The sense amplifier driver includes a plurality of drive circuits each coupled to the first and second activation nodes of the sense amplifiers in at least one of the memory-cell arrays. The first activation nodes of the sense amplifiers in at least one of the memory-cell arrays are coupled to a plurality of drive circuits so that the plurality of drive circuits drive the first activation nodes of the sense amplifiers in at least one of the memory-cell arrays in parallel.

Abstract: A DRAM is stress tested by writing a logic bit in a weakened state from a sense amplifier of the DRAM to a sub-array of the DRAM. This is accomplished by reducing an upper rail voltage supplied to a P-sense amp in the sense amplifier and increasing a lower rail voltage supplied to an N-sense amp in the sense amplifier, or by operating isolation NMOS transistors through which a differential voltage representative of the logic bit passes from the sense amplifier to the sub-array at less than a full activation level. Once the logic bit is written to the sub-array in a weakened state, it is then read back out to stress the DRAM and thereby identify weak sense amplifiers and DRAM cells in the DRAM.

Abstract: A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state.

Abstract: A memory array architecture is described which uses active digit lines at array edges. To maximize array area using active digit lines, a memory array architecture is employed where interior rows of memory cells intersect X columns of memory cells. Rows located along the edge of the array, however, intersect less than X columns of memory cells. Two rows of memory cells located along the edge of the array must be accessed together to form a complete row of X columns.

Abstract: A sense amplifier senses a small voltage differential across true and complementary digit lines in a dynamic random access memory (DRAM) integrated circuit. The sensed voltage is further separated and amplified into full logic levels. Activating the P-sense amplifier before the N-sense amplifier speeds sensing. The P-sense amplifier control signal is capacitively coupled to each of the true and complementary digit lines. The P-sense amplifier further increases the more positive digit line to the power supply voltage V.sub.cc. The other digit line is at a voltage more positive than its equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier, particularly for low values of V.sub.cc, in which the threshold voltages of the NFETs in the N-sense amplifier are close to the equilibration voltage. Capacitor elements need not be added to the sense amplifier layout.

Abstract: A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

Abstract: A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state.

Abstract: A memory architecture includes a matrixed arrangement of memory cell arrays having interstitial separations bounding each memory cell array. The interstitial separations between memory cell arrays include longitudinal streets, carrying row decoders, and latitudinal streets, carrying column decoders that include sense amplifiers. Decoder control circuits are disposed in the intersections of the longitudinal and latitudinal streets. Each decoder control circuit includes drivers for providing addressing or other signals to pairs of adjacent row or column decoders. Each driver provides a signal to more than one decoder, such as to each of the row or column decoders between which the decoder control circuit is interposed. The decoder control circuit requires fewer drivers, which can be staggered or laterally offset to better accommodate magnitude reductions of the interstitial separations between memory cell arrays, thereby increasing storage density.

Abstract: Memory devices, such as random access memory, are affixed to an electrical contact frame and coupled to signals lines on the contact frame which is, in turn, mounted on a top surface of an integrated circuit. The signal leads are coupled to electrical contact pads disposed on the top surface of the integrated circuit. The contact pads and signal leads transfer control and power signals between the integrated circuit and the memory devices.

Abstract: A memory device that uses a dynamic cell plate sensing scheme. The memory device includes an array of word lines and complementary bit line/plate line pairs. A number of memory cells are located at the intersection of selected word lines and bit line/plate line pairs. A sense amplifier is coupled to the complementary bit line/plate line pairs. The memory device also includes an equilibrate circuit that ac equilibrates a complementary bit line/plate line pair at an equilibration voltage between high and low logic levels prior to reading data. The equilibration voltage and the high and low logic levels for the memory cell are chosen such that a fluctuation in the voltage on one of the plate lines does not corrupt data stored in unaccessed memory cells coupled to the same plate line.

Abstract: A memory array architecture is described which uses active digit lines at array edges. To maximize array area using active digit lines, a memory array architecture is employed where interior rows of memory cells intersect X columns of memory cells. Rows located along the edge of the array, however, intersect less than X columns of memory cells. Two rows of memory cells located along the edge of the array must be accessed together to form a complete row of X columns.

Abstract: A dynamic integrated circuit memory is described which has memory cells arranged in rows. The memory rows are selectively accessible using an addressing circuit and local phase lines. Distributed local phase driver circuits are used to drive the local phase lines to a pumped voltage which are coupled to the gate of a memory cell access transistor. Addressing circuitry is provided to selectively address the distributed local phase driver circuits.

Abstract: A sense amplifier senses a small voltage differential across true and complementary digit lines in a dynamic random access memory (DRAM) integrated circuit. The sensed voltage is further separated and amplified into full logic levels. Activating the P-sense amplifier before the N-sense amplifier speeds sensing. The P-sense amplifier control signal is capacitively coupled to each of the true and complementary digit lines. The P-sense amplifier further increases the more positive digit line to the power supply voltage V.sub.cc. The other digit line is at a voltage more positive than its equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier, particularly for low values of V.sub.cc, in which the threshold voltages of the NFETs in the N-sense amplifier are close to the equilibration voltage. Capacitor elements need not be added to the sense amplifier layout.

Abstract: A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state.

Abstract: A dynamic integrated circuit memory is described which has memory cells arranged in rows. The memory rows are selectively accessible using an addressing circuit and local phase lines. Distributed local phase driver circuits are used to drive the local phase lines to a pumped voltage which are coupled to the gate of a memory cell access transistor. Addressing circuitry is provided to selectively address the distributed local phase driver circuits.

Abstract: A precharge circuit which is deactivated once a word line driver is activated. Specifically, a low output signal created by the selected driver is fed back to the precharge circuit to deactivate the precharge circuit during activation of a chosen word line.

Abstract: A power-up circuit in a computer system drives a memory device such as a dynamic random access memory (DRAM) to an initial condition after the computer system is turned on or reset. The power-up circuit also advantageously drives the memory device into the initial condition upon detecting a transient such as a negative glitch in a supply voltage being provided to the memory device. The power-up circuit includes a voltage level detector which causes a power-up signal to be provided to the memory device upon detecting that the supply voltage is less than a threshold voltage of the memory device which is necessary for the memory device to operate in an operational state.

Abstract: There is a precharge circuitry that uses little real estate and can be deactivated once a word line driver is activated. Specifically, a high signal created by the selected driver is fed back to the precharge circuit to deactivate it when activating a chosen word line. Thus, alleviating the resulting effect between the low signal to activate the selected driver and the precharge high voltage current both using the same node coupled to the word line drivers.