Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Abstract: A memory device is provided. The memory device comprises a memory array and circuitry configured to determine one or more settings for the memory array corresponding to a powered-on state of the memory device, to store the one or more settings in a non-volatile memory location, and in response to returning to the powered-on state from a reduced-power state, to read the one or more settings from the non-volatile memory location.

Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Methods and apparatuses are disclosed including an apparatus that includes a controller circuit configured to access a first subarray of a memory and to access a second subarray of the memory subsequent to accessing the first subarray but contemporaneous with precharging a portion of the first subarray by a precharge circuit associated with the first subarray.

Abstract: The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock can be selectively gated in response to a gating signal based in part on idle time and absence of a read or write burst operation. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.

Abstract: The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock can be selectively gated in response to a gating signal based in part on idle time and absence of a read or write burst operation. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.