Abstract: A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state.

Abstract: A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit, provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state.

Abstract: A memory-cell array includes several memory cells arranged in rows and columns. The memory cells in each row include an access terminal coupled to an associated word line. The memory cells in each column are coupled between a respective first digit line and a respective complementary digit line. The complementary digit line is divided into several portions. A sense amplifier has first and second data terminals with the first data terminal coupled to the first digit line. The memory-cell array includes several first isolation devices, each first isolation device selectively coupling an associated portion of the complementary digit line to the second data terminal of the sense amplifier.

Abstract: A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

Abstract: Memory devices, such as random access memory, are affixed to an electrical contact frame and coupled to signals lines on the contact frame which is, in turn, mounted on a top surface of an integrated circuit. The signal leads are coupled to electrical contact pads disposed on the top surface of the integrated circuit. The contact pads and signal leads transfer control and power signals between the integrated circuit and the memory devices.

Abstract: A memory architecture includes a matrixed arrangement of memory cell arrays having interstitial separations bounding each memory cell array. The interstitial separations between memory cell arrays include longitudinal streets, carrying row decoders, and latitudinal streets, carrying column decoders that include sense amplifiers. Decoder control circuits are disposed in the intersections of the longitudinal and latitudinal streets. Each decoder control circuit includes drivers for providing addressing or other signals to pairs of adjacent row or column decoders. Each driver provides a signal to more than one decoder, such as to each of the row or column decoders between which the decoder control circuit is interposed. The decoder control circuit requires fewer drivers, which can be staggered or laterally offset to better accommodate magnitude reductions of the interstitial separations between memory cell arrays, thereby increasing storage density.

Abstract: A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state.

Abstract: A memory architecture includes a matrixed arrangement of memory cell arrays having interstitial separations bounding each memory cell array. The interstitial separations between memory cell arrays include longitudinal streets, carrying row decoders, and latitudinal streets, carrying column decoders that include sense amplifiers. Decoder control circuits are disposed in the intersections of the longitudinal and latitudinal streets. Each decoder control circuit includes drivers for providing addressing or other signals to pairs of adjacent row or column decoders. Each driver provides a signal to more than one decoder, such as to each of the row or column decoders between which the decoder control circuit is interposed. The decoder control circuit requires fewer drivers, which can be staggered or laterally offset to better accommodate magnitude reductions of the interstitial separations between memory cell arrays, thereby increasing storage density.

Abstract: A latch circuit provides an equilibration voltage to a plurality of equilibrate circuits in a memory device. If a row to column short occurs which draws too much current from the latch circuit, the latch circuit will change states and cease supplying a voltage to the equilibrate circuit, thereby limiting current drain on the memory device.

Abstract: A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

Abstract: An equilibration circuit for a memory device that prevents excessive current from being drawn by the memory device when a row to column short exists while still allowing the use of segmented column repair is disclosed. Each equilibration circuit of a memory device is connected to the equilibration voltage through a transistor that is controlled by a pulsed signal. When the pulsed signal is high, the transistor will turn on, connecting the digital lines to the equilibration voltage to pre-charge the digit lines to the equilibration voltage. The pulse duration is short enough, however, to turn the transistor off before the equilibration voltage can be pulled down if a column to row short exists.

Abstract: A low voltage power-up detection circuit for use includes a programmable resistance biasing network which provides an adjustable voltage to vary a power-up voltage detection point. The programming of the bias network can be set during testing of the device. The low voltage power-up detection circuit may be used with many devices including memory devices such as DRAMs.

Abstract: A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

Abstract: A semiconductor memory device is disclosed that can be operated in a speed test mode. The memory device includes an array of memory cells capable of storing data, a control circuit receiving a signal from an external system clock and controlling data transfer operations between the memory device and an external data bus, and a test mode circuit receiving the external clock signal. When operated in speed test mode, the control circuit provides a signal to the test mode circuit enabling its function. A predetermined data pattern is first written to one or more cells, and then subsequently accessed during a read cycle. The enabled test mode circuit compares the contents of an internal data bus to the predetermined data pattern at a time referenced to the system clock signal. In the case of a failed comparison, the test mode circuit produces a signal that places the external data bus in a high impedance state.

Abstract: Memory devices, such as random access memory, are affixed to an electrical contact frame and coupled to signals lines on the contact frame which is, in turn, mounted on a top surface of an integrated circuit. The signal leads are coupled to electrical contact pads disposed on the top surface of the integrated circuit. The contact pads and signal leads transfer control and power signals between the integrated circuit and the memory devices.

Abstract: Memory devices, such as random access memory, are affixed to an electrical contact frame and coupled to signals lines on the contact frame which is, in turn, mounted on a top surface of an integrated circuit. The signal leads are coupled to electrical contact pads disposed on the top surface of the integrated circuit. The contact pads and signal leads transfer control and power signals between the integrated circuit and the memory devices.

Abstract: A DRAM is stress tested by writing a logic bit in a weakened state from a sense amplifier of the DRAM to a sub-array of the DRAM. This is accomplished by reducing an upper rail voltage supplied to a P-sense amp in the sense amplifier and increasing a lower rail voltage supplied to an N-sense amp in the sense amplifier, or by operating isolation NMOS transistors through which a differential voltage representative of the logic bit passes from the sense amplifier to the sub-array at less than a full activation level. Once the logic bit is written to the sub-array in a weakened state, it is then read back out to stress the DRAM and thereby identify weak sense amplifiers and DRAM cells in the DRAM.

Abstract: A memory device that uses a dynamic cell plate sensing scheme. The memory device includes an array of word lines and complementary bit line/plate line pairs. A number of memory cells are located at the intersection of selected word lines and bit line/plate line pairs. A sense amplifier is coupled to the complementary bit line/plate line pairs. The memory device also includes an equilibrate circuit that ac equilibrates a complementary bit line/plate line pair at an equilibration voltage between high and low logic levels prior to reading data. The equilibration voltage and the high and low logic levels for the memory cell are chosen such that a fluctuation in the voltage on one of the plate lines does not corrupt data stored in unaccessed memory cells coupled to the same plate line.

Abstract: A memory architecture includes a matrixed arrangement of memory cell arrays having interstitial separations bounding each memory cell array. The interstitial separations between memory cell arrays include longitudinal streets, carrying row decoders, and latitudinal streets, carrying column decoders that include sense amplifiers. Decoder control circuits are disposed in the intersections of the longitudinal and latitudinal streets. Each decoder control circuit includes drivers for providing addressing or other signals to pairs of adjacent row or column decoders. Each driver provides a signal to more than one decoder, such as to each of the row or column decoders between which the decoder control circuit is interposed. The decoder control circuit requires fewer drivers, which can be staggered or laterally offset to better accommodate magnitude reductions of the interstitial separations between memory cell arrays, thereby increasing storage density.

Abstract: A memory device that uses a dynamic cell plate sensing scheme. The memory device includes an array of word lines and complementary bit line/plate line pairs. A number of memory cells are located at the intersection of selected word lines and bit line/plate line pairs: A sense amplifier is coupled to the complementary bit line/plate line pairs. The memory device also includes an equilibrate circuit that ac equilibrates a complementary bit line/plate line pair at an equilibration voltage between high and low logic levels prior to reading data. The equilibration voltage and the high and low logic levels for the memory cell are chosen such that a fluctuation in the voltage on one of the plate lines does not corrupt data stored in unaccessed memory cells coupled to the same plate line.