Abstract: A carrier aggregation front-end module with a receive sub-module for receiving signals from a plurality of transmit modules. The module comprises a first receive path configured to receive a first set of signals from one or more of a plurality of antennas, wherein the first set of signals comprises at least one desired receive signal and at least one undesired transmit blocker signal from the plurality of transmit modules. The second receive path is configured to receive a second set of signals from one or more of a plurality of antennas comprising at least one desired receive signal and at least one undesired transmit blocker signal from the plurality of transmit modules. The module also comprises at least one shared tunable notch filter configured to reject at least one of the undesired transmit blocker signals for each of the first receive path and the second receive path.

Abstract: Embodiments of radio frequency (RF) filtering circuitry are disclosed. In one embodiment, the RF filtering circuitry includes a first port, a second port, a first RF filter path, and a second RF filter path. The first RF filter path is connected between the first port and the second port and includes at least a pair of weakly coupled resonators. The weakly coupled resonators are configured such that a first transfer response between the first port and the second port defines a first passband. The second RF filter path is coupled to the first RF filter path and is configured such that the first transfer response between the first port and the second port defines a stopband adjacent to the first passband without substantially increasing ripple variation of the first passband defined by the first transfer response.

Abstract: RF switching circuitry includes a plurality of FETs coupled between an input node, an output node, and a gate drive node. When a positive power supply voltage is provided at the gate drive node, the plurality of FETs turn on and provide a low impedance path between the input node and the output node. When a negative power supply voltage is provided at the gate drive node, the plurality of FETs turn off and provide a high impedance path between the input node and the output node. Switch acceleration circuitry in the RF switching circuitry includes a bypass FET and multi-level driver circuitry. The bypass FET selectively bypasses the common resistor in response to a multi-level drive signal. The multi-level driver circuitry uses a built-in gate to capacitance of the bypass FET to provide the multi-level drive signal at an overvoltage that is above the positive power supply voltage.

Abstract: Alternating Current (AC)-coupled switch and metal capacitor structures for nanometer or low metal layer count processes are provided. According to one aspect of the present disclosure, a switch and capacitor structure comprises a substrate comprising a device region with a Field Effect Transistor (FET) formed therein, the FET having a source terminal comprising a structure in a first metal layer and a drain terminal comprising a structure in the first metal layer, and a capacitor comprising a first plate and a second plate, the first plate comprising a structure in a second metal layer, the second metal layer being above the first metal layer, the structure of the first plate being electrically connected to the structure of the drain terminal, and the second plate comprising a structure in the second metal layer, the structure of the first plate spaced from the structure of the second plate.

Abstract: Embodiments of radio frequency (RF) filtering circuitry are disclosed. In one embodiment, the RF filtering circuitry includes a common port, a second port, a third port, a first RF filter path, and a second RF filter path. The first RF filter path is connected between the common port and the second port and comprises a first pair of resonators and a first acoustic wave resonator. One of the first pair of resonators also includes a second acoustic wave resonator. The second RF filter path is connected between the common port and the third port. The second RF filter path includes a second pair of resonators. The first and second acoustic wave resonators of the first RF filter path increase roll-off greatly with respect to just an LC filter, and thereby allow for an increase out-of-band rejection at high frequency ranges.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: The present disclosure relates to a transmission line structure embedded in a back-end-of-line (BEOL) body that has a cavity. The transmission line structure includes a signal transmission line, a ground plane and a shielding line. The signal transmission line and the first shielding line are formed on a same metallization level, and the ground plane is formed underneath and electrically connected to the first shielding line. A side surface of the signal transmission line and a side surface of the first shielding line, which faces the side surface of the signal transmission line, are exposed to the cavity of the BEOL body, and not covered by any high resistivity conductive coating.

Abstract: A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells includes a field-effect transistor having a drain terminal, a source terminal, a FET gate terminal, and a body terminal and an off-state linearization network. The off-state linearization network includes varactors coupled to the drain terminal and the source terminal of the field-effect transistor.

Abstract: A semiconductor die including a substrate, a device layer over the substrate, and an adjustable component in the device layer is provided, where a surface of the device layer opposite the substrate is the frontside of the semiconductor die. At least a portion of the substrate is removed to expose a backside of the semiconductor die opposite the frontside. The adjustable component is then trimmed through the backside of the semiconductor die.

Abstract: An RF switch having an M number of FETs that are stacked in series and coupled between a first end node and a second end node wherein each of the M number of FETs has a gate is disclosed. A resistive network is coupled between a common mode (CM) node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal. Biasing circuitry coupled to the CM node is configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: A radio frequency switch having a first node, a second node, and a plurality of switch cells that are coupled in series between the first node and the second node is disclosed. Each of the plurality of switch cells is made up of a main field-effect transistor (FET) having a main drain terminal, a main source terminal, a main gate terminal, and a main body terminal. Further included is a first body bias FET having a first drain terminal coupled to the main gate terminal, a first gate terminal coupled to the main drain terminal, a first body terminal coupled to the main body terminal, and a first source terminal, and a second body bias FET having a second drain terminal coupled to the main gate terminal, a second body terminal coupled to the main body terminal, and a second source terminal coupled to the first source terminal.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: Embodiments of the disclosure relate to a three-dimensional (3D) inductor-capacitor (LC) circuit. The 3D LC circuit includes an inductor formed by a conductive ribbon of a defined height and a conductive sleeve conductively coupled to the conductive ribbon. The conductive sleeve and the conductive ribbon can generate a built-in capacitance(s) for the 3D LC circuit. In examples discussed herein, the conductive ribbon can also help reduce the skin effect of the inductor by distributing an electrical current across the defined height of the conductive ribbon. By generating the built-in capacitance(s) and distributing the electrical current across the defined height of the conductive ribbon, it is possible to reduce current crowding and improve quality factor (Q-factor) of the 3D LC circuit. As a result, it is possible to couple one or more 3D LC circuits to form a high performance radio frequency (RF) filter(s) for the fifth-generation (5G) wireless communication systems.

Abstract: A semiconductor die including a substrate, a device layer over the substrate, and an adjustable component in the device layer is provided, where a surface of the device layer opposite the substrate is the frontside of the semiconductor die. At least a portion of the substrate is removed to expose a backside of the semiconductor die opposite the frontside. The adjustable component is then trimmed through the backside of the semiconductor die.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: Dynamic error vector magnitude (EVM) compensation is accomplished for radio frequency (RF) power amplifiers (PAs) which experience EVM distortion from thermal settling. Thermal settling causes gain changes in the PAs, and systems, apparatuses, and methods of the present disclosure compensate for known thermal transients of PAs.