Abstract: A coupled inductor structure includes a first three-dimensional inductor structure and a second three-dimensional folded inductor structure. At least a portion of the first three-dimensional folded inductor structure is located within a volume bounded by the second three-dimensional folded inductor structure. By nesting the first three-dimensional folded inductor structure within the second three-dimensional folded inductor structure, a variety of coupling factors can be achieved while minimizing the size of the coupled inductor structure.

Abstract: A power amplifier system is disclosed. The power amplifier system includes a power amplifier having a first signal input and a first signal output and a main bias circuitry configured to provide a first portion of a first bias signal to the power amplifier through a first bias output coupled to the first signal input. Further included is peak bias circuitry that is configured to provide a second portion of the first bias signal to the power amplifier through a second bias output coupled to the first signal input, wherein the first portion of the first bias signal is greater than the second portion of the first bias signal over a first input power range and the second portion of the first bias signal is greater than the first portion of the first bias signal over a second input power range that is greater than the first input power range.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A broadband power amplifier circuit is provided. The broadband power amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal to an output power based on a bias voltage and a supply voltage. Given that the output power of the RF signal may rise and fall from time to time, the broadband power amplifier circuit is configured to opportunistically increase or decrease the bias voltage in a defined future time (e.g., a future time slot or a future symbol duration) based on the output power in the defined future time. When necessary, the broadband power amplifier may be further configured to adjust the supply voltage and/or attenuate the RF signal based on the output power. As such, it may be possible to maintain class-A operation mode for the amplifier circuit. As a result, the amplifier circuit may maintain linearity and avoid memory effect with improved efficiency.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: A radio frequency switch made up of a plurality of switch cells coupled in series between a first node and a second node is disclosed. Each of the plurality of switch cells has a switch field-effect transistor (FET) having a switch drain terminal, a switch source terminal, a switch gate terminal, and a switch body terminal. A body bias network having a first body bias FET with a first drain terminal coupled to the switch body terminal includes a first cross-FET with a second drain terminal coupled to a first source terminal of the first bias body FET and a second source terminal coupled to the switch gate terminal. A second body bias FET has a third drain terminal coupled to the switch body terminal, and a second cross-FET has a fourth drain terminal coupled to a third source terminal of the second body bias FET.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: A low-noise amplifier system is disclosed. The low-noise amplifier system includes a low-noise amplifier having an input node and an output node in a receive path and a capacitance equalization network coupled to the output node. Compensation capacitance of the capacitance equalization network sums with non-linear capacitance of the low-noise amplifier such that a total capacitance at the output node varies by no more than ±5% over an output voltage range within voltage headroom limits of the low-noise amplifier for a given supply voltage of the low-noise amplifier. In at least some exemplary embodiments, the compensation capacitance of the capacitance equalization network is a function of output signal voltage at the output node.

Abstract: The present disclosure relates to a transmission line structure embedded in a back-end-of-line (BEOL) body that has a cavity. The transmission line structure includes a signal transmission line, a ground plane and a shielding line. The signal transmission line and the first shielding line are formed on a same metallization level, and the ground plane is formed underneath and electrically connected to the first shielding line. A side surface of the signal transmission line and a side surface of the first shielding line, which faces the side surface of the signal transmission line, are exposed to the cavity of the BEOL body, and not covered by any high resistivity conductive coating.

Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

Abstract: A transistor-based radio frequency (RF) switch that provides symmetric RF impedance is disclosed. The transistor-based RF switch includes an N number of main field-effect transistors (FETs) stacked in series between a first end node and a second end node. A first end-network is coupled between the first end node and a proximal gate node. The first end-network provides a first variable impedance that equalizes a drain-to-source voltage of the first main FET to within a predetermined percentage of a drain-to-source voltage of a second main FET of the N number of main FETs. A second end-network is coupled between the second end node and the distal gate node, wherein the second end-network provides a second variable impedance to equalize the drain-to-source voltage of an Nth main FET to within the predetermined percentage of the drain-to-source voltage of an N?1 main FET of the N number of main FETs.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: Power amplifier (PA) output memory neutralization is disclosed, using baseband input/output (I/O) capacitance current compensation. Radio frequency (RF) PAs experience I/O memory effects when used with envelope tracking supply modulation schemes. Envelope tracking supply modulation results in a nonlinear variation of the I/O capacitance. Traditional approaches compensate for such effects with a current provided by a bias circuit which is band-limited. This results in memory effects which distort the amplified signal, becoming more significant as the modulation bandwidth increases. An RF communications system according to embodiments disclosed herein mitigates such memory effects by compensating for the non-linear effect of the I/O capacitance in an RF PA.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

Abstract: Embodiments of the disclosure relate to a three-dimensional (3D) inductor-capacitor (LC) circuit. The 3D LC circuit includes an inductor formed by a conductive ribbon of a defined height and a conductive sleeve conductively coupled to the conductive ribbon. The conductive sleeve and the conductive ribbon can generate a built-in capacitance(s) for the 3D LC circuit. In examples discussed herein, the conductive ribbon can also help reduce the skin effect of the inductor by distributing an electrical current across the defined height of the conductive ribbon. By generating the built-in capacitance(s) and distributing the electrical current across the defined height of the conductive ribbon, it is possible to reduce current crowding and improve quality factor (Q-factor) of the 3D LC circuit. As a result, it is possible to couple one or more 3D LC circuits to form a high performance radio frequency (RF) filter(s) for the fifth-generation (5G) wireless communication systems.

Abstract: A radio frequency switch made up of a plurality of switch cells coupled in series between a first node and a second node is disclosed. Each of the plurality of switch cells has a switch field-effect transistor (FET) having a switch drain terminal, a switch source terminal, a switch gate terminal, and a switch body terminal. A body bias network having a first body bias FET with a first drain terminal coupled to the switch body terminal includes a first cross-FET with a second drain terminal coupled to a first source terminal of the first bias body FET and a second source terminal coupled to the switch gate terminal. A second body bias FET has a third drain terminal coupled to the switch body terminal, and a second cross-FET has a fourth drain terminal coupled to a third source terminal of the second body bias FET.

Abstract: Embodiments of an apparatus that includes a substrate and an inductor residing in the substrate are disclosed. In one embodiment, the inductor is formed as a conductive path that extends from a first terminal to a second terminal. The conductive path has a shape corresponding to a two-dimensional (2D) lobe laid over a three-dimensional (3D) volume. Since the shape of the conductive path corresponds to the 2D lobe laid over a 3D volume, the magnetic field generated by the inductor has magnetic field lines that are predominately destructive outside the inductor and magnetic field lines that are predominately constructive inside the inductor. In this manner, the inductor can maintain a high quality (Q) factor while being placed close to other components.

Abstract: A multi-layer antenna assembly and related antenna array are provided. In one aspect, a multi-layer antenna assembly includes a first radiating layer(s) and a second radiating layer(s). The second radiating layer(s) is provided below and in parallel to the first radiating layer(s). The second radiating layer(s) overlaps at least partially with the first radiating layer(s). In this regard, an electromagnetic wave radiated vertically from the second radiating layer(s) is horizontally guided by an overlapping portion of the first radiating layer(s). In another aspect, an antenna array can be configured to include a number of multi-layer antenna assemblies to enable radio frequency (RF) beamforming. By employing the multi-layer antenna assemblies in the antenna array, it may be possible to flexibly and naturally steer an RF beam in a desired direction(s) without causing oversized side lobes, thus helping to improve power efficiency and performance of the antenna array.

Abstract: A Doherty amplifier system is disclosed. A main amplifier is configured to receive a first portion of a radio frequency (RF) signal at a main input and provide an amplified copy of the first portion of the RF signal at a main output. A peaking amplifier is configured to be controllably activated to receive a second portion of the RF signal at a peak input and provide an amplified copy of the second portion of the RF signal at a peak output. A saturation detector has a detector input coupled to the main output of the main amplifier and a first detector control output, wherein the saturation detector is configured to detect saturation of the main amplifier and activate the peaking amplifier as saturation of the main amplifier is detected and deactivate the peaking amplifier when saturation of the main amplifier is not detected by the saturation detector.