Patents by Inventor George Vergis

George Vergis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION FOR REFRESH OF MEMORY DEVICES ON A MEMORY MODULE
    Publication number: 20200027500
    Abstract: Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Douglas HEYMANN, Wei P. CHEN, Suresh CHITTOR, George VERGIS
  • Codeset communication format and related methods and structures
    Patent number: 10490064
    Abstract: A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 26, 2019
    Assignee: Universal Electronics Inc.
    Inventor: George Vergis
  • TECHNIQUES TO MIRROR A COMMAND/ADDRESS OR INTERPRET COMMAND/ADDRESS LOGIC AT A MEMORY DEVICE
    Publication number: 20190354132
    Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.
    Type: Application
    Filed: June 3, 2019
    Publication date: November 21, 2019
    Inventors: George VERGIS, Kuljit S. BAINS, Bill NALE
  • Memory channel having more than one DIMM per motherboard DIMM connector
    Patent number: 10467160
    Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Xiang Li, Yunhui Chu, Jun Liao, George Vergis, James A. McCall, Charles C. Phares, Konika Ganguly, Qin Li
  • Load reduced nonvolatile memory interface
    Patent number: 10459855
    Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Emily Chung, Frank T. Hady, George Vergis
  • CONNECTOR WITH ANCHORING POWER PIN
    Publication number: 20190296462
    Abstract: Anchoring power pins are described herein. In one embodiment, a system includes a circuit board including a through hole, and a connector for coupling a module with the circuit board. The connector includes housing including a module-facing side to receive the module and a circuit board-facing side to couple with the circuit board. The connector includes a conductive power pin to both physically anchor the connector to the circuit board and electrically couple the module with the circuit board, the conductive power pin including a tip protruding from the circuit board-facing side of the connector to extend into a matching through hole in the circuit board.
    Type: Application
    Filed: July 31, 2017
    Publication date: September 26, 2019
    Inventors: Xiang LI, George VERGIS
  • RETENTION OF DUAL IN-LINE MEMORY MODULES
    Publication number: 20190281719
    Abstract: Embodiments are directed towards apparatuses, methods, and systems for a memory module, e.g., a dual in-line memory module (DIMM) including a first lengthwise edge along the DIMM and a second lengthwise edge, opposite the first lengthwise edge, to couple the DIMM with a printed circuit board (PCB). In embodiments, the DIMM includes one or more notches along the first lengthwise edge, to removeably couple with one or more flexible supports located at least partially along a length or width of a chassis and to engage the notches to assist in retention of the DIMM in the chassis to reduce a shock and/or vibration associated with a load of a plurality of DIMMs on the PCB. In some embodiments, the one or more flexible supports are coupled to a support structure, such as a pole mounted or otherwise coupled to a panel of the chassis. Additional embodiments may be described and claimed.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Phil Geng, George Vergis, Xiang Li
  • CROSSTALK REDUCING CONNECTOR PIN GEOMETRY
    Publication number: 20190245309
    Abstract: Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 8, 2019
    Inventors: Jaejin Lee, Jun Liao, Xiang Li, George Vergis, Christopher E. Cox
  • TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MULTIPLE DATA CHANNELS
    Publication number: 20190213148
    Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
    Type: Application
    Filed: December 3, 2018
    Publication date: July 11, 2019
    Inventors: Bill NALE, Christopher E. COX, Kuljit S. BAINS, George VERGIS, James A. McCALL, Chong J. ZHAO, Suneeta SAH, Pete D. VOGT, John R. GOLES
  • Memory device with insertable portion
    Patent number: 10342132
    Abstract: Embodiments of the present disclosure are directed towards a memory device insertable into a PCB, e.g., a motherboard of a computing device. In some embodiments, the memory device may include a first PCB having a first thickness, to house one or more memory modules disposed on at least one side of the first PCB. The memory device may further include a layer having a second thickness, which may be attached to the side of the first PCB in an area that is proximate to an edge of the first PCB, to form a memory device portion that may be insertable into a connector slot disposed on a second PCB. The insertable portion may have a thickness that comprises the first and second thicknesses, to fit into the connector slot of the second PCB. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Xiang Li, George Vergis, Slobodan Mrdjan
  • EXTENDED MODE (XM) BUS MODE CHANGE, CONFIGURATION REGISTER ACCESSES AND BROADCAST / MULTI-CAST TRANSACTIONS TO DEVICES ON A XM BUS
    Publication number: 20190188165
    Abstract: In embodiments, a device includes an input interface to receive a broadcast command from a host computer, the broadcast command including an access mode indication, and decoding circuitry coupled with the interface. The decoding circuitry is to determine, based at least in part on the received access mode indication, that the broadcast command is directed to access one or more pre-defined setup or control registers of one or more devices, or to access one or more internal registers of the one or more devices, and, in response to the determination, implement the access to the setup or control registers, or to the one or more internal registers. In embodiments, the device is disposed on a memory module coupled to the host computer.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Inventors: Girish C. Venkatraman, Rajesh Bhaskar, George Vergis, John R. Goles
  • Techniques to mirror a command/address or interpret command/address logic at a memory device
    Patent number: 10310547
    Abstract: Techniques to include a mirror of a command/address at a memory device. Techniques to also include interpretation of command/address logic. A memory device located on a dual in-line memory module (DIMM) includes circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: George Vergis, Kuljit S. Bains, Bill Nale
  • CONNECTOR WITH RELAXATION MECHANISM FOR LATCH
    Publication number: 20190165503
    Abstract: An embodiment of a connector housing for a circuit board may include a connector body to receive the circuit board, and a relaxation mechanism mechanically coupled to the connector body to relax stress on the connector housing and maintain the circuit board received in the connector body under a load which exceeds a load threshold. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 1, 2019
    Publication date: May 30, 2019
    Inventors: Phil Geng, Xiang Li, George Vergis, Mani Prakash
  • Connector design for high density platforms
    Patent number: 10305207
    Abstract: A surface mount connector includes a housing including inner surfaces surrounding a card edge region, and outer surfaces defining an exterior region. The connector also includes a recess in at least one of the outer surfaces, the recess sized to accept a removably engageable arm therein. The connector also defines a cross-sectional width that is smaller in the recess than at a position adjacent to the recess. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 28, 2019
    Assignee: INTEL CORPORATION
    Inventors: Xiang Li, George Vergis
  • CODESET COMMUNICATION FORMAT AND RELATED METHODS AND STRUCTURES
    Publication number: 20190147735
    Abstract: A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Inventor: George Vergis
  • APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE
    Publication number: 20190139592
    Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package.
    Type: Application
    Filed: October 31, 2018
    Publication date: May 9, 2019
    Inventors: Kuljit S. BAINS, George VERGIS, James A. McCALL, Ge Chang
  • System for improved power distribution to a memory card through remote sense feedback
    Patent number: 10276219
    Abstract: In one embodiment, an apparatus comprises a first connector to couple to a connector of a memory card, the memory card comprising a first sense node to sense a supply voltage at a first location of the memory card, the first connector comprising a voltage supply pin; a ground pin; and a sense pin to couple to the first sense node; a first sense line to couple to the first sense node through the sense pin; and a voltage regulator coupled to the first sense line, the voltage regulator to provide the supply voltage based on feedback received from the first sense node of the memory card via the first sense line.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: George Vergis, Dat Le
  • MEMORY CHANNEL HAVING MORE THAN ONE DIMM PER MOTHERBOARD DIMM CONNECTOR
    Publication number: 20190102331
    Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Xiang LI, Yunhui CHU, Jun LIAO, George VERGIS, James A. McCALL, Charles C. PHARES, Konika GANGULY, Qin LI
  • THERMAL SOLUTION ON LATCH FOR SODIMM CONNECTOR
    Publication number: 20190103690
    Abstract: Embodiments include devices, systems, and methods relating to removing heat from a memory module in a connector. One embodiment relates to a memory module connector comprising a first arm, a second arm, and a body portion positioned between the first arm and the second arm, the body portion configured to accept a memory module therein. The memory module connector includes a structure coupled to the first arm and configured to be electrically coupled to a printed circuit board. The memory module connector also includes a heat spreader coupled to the first arm, the heat spreader configured to be brought into thermal contact with a memory module component. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Xiang LI, George VERGIS, Douglas HEYMANN
  • BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM SLOTS AND APPLICATIONS THEREOF
    Publication number: 20190042162
    Abstract: A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.
    Type: Application
    Filed: August 16, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporationn
    Inventors: James A. McCALL, Suneeta SAH, George VERGIS, Dimitrios ZIAKAS, Bill NALE, Chong J. ZHAO, Rajat AGARWAL