Patents by Inventor George Vergis

George Vergis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit board with a connector having a latch that includes a latch frame, a latch slide, an ejector and a connector arm
    Patent number: 9935384
    Abstract: A circuit board may include a connector having a circuit module latch that may include a latch frame and pivot-able ejector assembly coupled to the latch frame.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Xiang Li, George Vergis, John M. Lynch
  • CIRCUIT BOARD WITH A CONNECTOR HAVING A LATCH THAT INCLUDES A LATCH FRAME, A LATCH SLIDE, AN EJECTOR AND A CONNECTOR ARM
    Publication number: 20180090862
    Abstract: A circuit board may include a connector having a circuit module latch that may include a latch frame and pivot-able ejector assembly coupled to the latch frame.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Xiang Li, George Vergis, John M. Lynch
  • Dynamic linking of codesets in universal remote control devices
    Patent number: 9918034
    Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 13, 2018
    Assignee: Universal Electronics Inc.
    Inventors: George Vergis, Sunilkumar Mankame
  • DOUBLE DATA RATE COMMAND BUS
    Publication number: 20180061478
    Abstract: A memory subsystem includes a command address bus capable to be operated at double data rate. A memory circuit includes N command signal lines that operate at a data rate of 2R to receive command information from a memory controller. The memory circuit includes 2N command signal lines that operate at a data rate of R to transfer the commands to one or more memory devices. While ratios of 1:2 are specified, similar techniques can be used to send command signals at higher data rates over fewer signal lines from a host to a logic circuit, which then transfers the command signals at lower data rates over more signal lines.
    Type: Application
    Filed: September 30, 2016
    Publication date: March 1, 2018
    Inventors: George VERGIS, Kuljit S. BAINS
  • TECHNIQUES TO ALLOCATE REGIONS OF A MULTI-LEVEL, MULTI-TECHNOLOGY SYSTEM MEMORY TO APPROPRIATE MEMORY ACCESS INITIATORS
    Publication number: 20180032429
    Abstract: A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with a respective region of the system memory having an appropriate latency and/or bandwidth.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventors: Min LIU, Zhenlin LUO, George VERGIS, Murugasamy K. NACHIMUTHU, Mohan J. KUMAR, Ross E. ZWISLER
  • HIGH PERFORMANCE PERSISTENT MEMORY
    Publication number: 20180032414
    Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 1, 2018
    Inventors: Mohan J. KUMAR, Murugasamy K. NACHIMUTHU, George VERGIS
  • LOAD REDUCED NONVOLATILE MEMORY INTERFACE
    Publication number: 20180004688
    Abstract: A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Emily CHUNG, Frank T. HADY, George VERGIS
  • DELAY-COMPENSATED ERROR INDICATION SIGNAL
    Publication number: 20180004592
    Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 4, 2018
    Inventors: Kuljit S. BAINS, George VERGIS
  • CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES
    Publication number: 20180007791
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 4, 2018
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • CPU package substrates with removable memory mechanical interfaces
    Patent number: 9832876
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • High performance persistent memory
    Patent number: 9792190
    Abstract: Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Mohan J. Kumar, Murugasamy K. Nachimuthu, George Vergis
  • Techniques to Mirror a Command/Address or Interpret Command/Address Logic at a Memory Device
    Publication number: 20170255404
    Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.
    Type: Application
    Filed: September 15, 2016
    Publication date: September 7, 2017
    Applicant: Intel Corporation
    Inventors: George Vergis, Kuljit S. Bains, Bill Nale
  • Delay-compensated error indication signal
    Patent number: 9710323
    Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Kuljit Singh Bains, George Vergis
  • Techniques to Access or Operate a Dual In-Line Memory Module via Multiple Data Channels
    Publication number: 20170199830
    Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
    Type: Application
    Filed: June 28, 2016
    Publication date: July 13, 2017
    Inventors: Bill Nale, Kuljit S. Bains, George Vergis, Christopher E. Cox, James A. McCall, Chong J. Zhao, Suneeta Sah, Pete D. Vogt, John R. Goles
  • Fast memory initialization
    Publication number: 20170185486
    Abstract: In an example, there is disclosed a memory controller, including: a data buffer to drive a determinate value to a data bus to communicatively couple to a memory; and a register clock driver to: receive a memory initialization command from a processor; and incrementally step through a plurality of initialization addresses, sequentially driving each initialization address to an address bus to communicatively couple to the memory. There is also disclosed a computing device comprising the memory controller, and a method of initializing memory comprising incrementally stepping through a plurality of initialization addresses and sequentially writing a determinate value to each address.
    Type: Application
    Filed: December 26, 2015
    Publication date: June 29, 2017
    Applicant: Intel Corporation
    Inventors: Mohan J. Kumar, George Vergis, Sarathy Jayakumar
  • DYNAMIC LINKING OF CODESETS IN UNIVERSAL REMOTE CONTROL DEVICES
    Publication number: 20170150084
    Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.
    Type: Application
    Filed: February 7, 2017
    Publication date: May 25, 2017
    Inventors: George Vergis, Sunilkumar Mankame
  • Techniques to communicate with a controller for a non-volatile dual in-line memory module
    Patent number: 9645829
    Abstract: Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 9, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sarathy Jayakumar, Mohan J. Kumar, Adam J. Brooks, George Vergis
  • Dynamic linking of codesets in universal remote control devices
    Patent number: 9621836
    Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: April 11, 2017
    Assignee: Universal Electronics Inc.
    Inventor: George Vergis
  • CODESET COMMUNICATION FORMAT AND RELATED METHODS AND STRUCTURES
    Publication number: 20170098369
    Abstract: A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventor: George Vergis
  • Codeset communication format and related methods and structures
    Patent number: 9582996
    Abstract: A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: February 28, 2017
    Assignee: Universal Electronics Inc.
    Inventor: George Vergis