Abstract: An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.

Abstract: In embodiments, a memory controller includes a sensor poller and a proportional integral controller (PIC) coupled to the sensor poller. The sensor poller is to obtain a temperature and a power of a memory module (MM) operated by the controller, and the PIC is to: dynamically set at least one bandwidth limit for the MM, based, at least in part, on a relationship between a temperature of the MM, a power of the MM and a bandwidth of the MM. In embodiments, the dynamically set bandwidth limit defines the power of the MM at which the MM operates for a predetermined temperature limit. In embodiments, a system includes a memory controller and a dual in-line memory module (DIMM) operated by it.

Abstract: A shielded SODIMM system for reducing RF emissions of a SODIMM connector is disclosed herein. SODIMM connector RFI presently interferes with connectivity and is also an obstacle for higher speed memory applications. The shielded SODIMM system includes a SODIMM connector that is at least partially housed by a SODIMM connector shield, to partially and/or substantially reduce or block RF emissions from the SODIMM connector. The SODIMM connector shield is at least partially conductive and is coupled to landing pads on a surface of a motherboard printed circuit board (“PCB”). The landing pads of the motherboard PCB that are coupled to the SODIMM connector shield are coupled to ground, which grounds the SODIMM connector shield. Grounding the SODIMM connector shield that at least partially houses the SODIMM connector reduces RF emissions from the SODIMM connector during information transfer operations.

Abstract: Various aspects are related to a connector, e.g., for connecting two boards with one another. The connector may include a housing and a plurality of pins. The housing may include a first housing surface and a second housing surface opposite the first housing surface. Each pin of the plurality of pins may include a first portion protruding arcuately from the first housing surface and a second portion protruding arcuately from the second housing surface.

Abstract: An apparatus is described. The apparatus includes a memory controller having register space to inform the memory controller that the memory controller is coupled to a memory module that conforms to a first memory chip industry standard specification but is composed of memory chips that conform to a second, different memory chip industry standard specification.

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

Abstract: A memory module connector includes a memory module receiving slot configured to receive a memory module. The memory module connector further includes a restraining mechanism configured to release the memory module if a force applied by the memory module to the restraining mechanism is above a pre-determined force threshold.

Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.

Abstract: Embodiments of the present disclosure are directed towards a memory device insertable into a PCB, e.g., a motherboard of a computing device. In some embodiments, the memory device may include a first PCB having a first thickness, to house one or more memory modules disposed on at least one side of the first PCB. The memory device may further include a layer having a second thickness, which may be attached to the side of the first PCB in an area that is proximate to an edge of the first PCB, to form a memory device portion that may be insertable into a connector slot disposed on a second PCB. The insertable portion may have a thickness that comprises the first and second thicknesses, to fit into the connector slot of the second PCB. Other embodiments may be described and/or claimed.

Abstract: A codeset is described in a Public Codeset Communication Format (PCCF) as a format block including a plurality of fields having readily decipherable values, such as ASCII character values. One field is a mark/space information field that includes a sequence of mark time indicators and space time indicators for an operational signal of the codeset. A second field is a signal characteristic information field for the operational signal. Signal characteristic information may include carrier on/off information, repeat frame information, toggle control information, and last frame information. The PCCF is a codeset interchange format of general applicability.

Abstract: A surface mount connector includes a housing including inner surfaces surrounding a card edge region, and outer surfaces defining an exterior region. The connector also includes a recess in at least one of the outer surfaces, the recess sized to accept a removably engageable arm therein. The connector also defines a cross-sectional width that is smaller in the recess than at a position adjacent to the recess. Other embodiments are described and claimed.

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

Abstract: One embodiment relates to a memory module connector comprising a housing defining a stepped slot configured to accept a memory module. Another embodiment includes a memory module defining a stepped slot configured to accept a memory module, and a memory module comprising a printed circuit board and a plurality of components mounted on the printed circuit board, wherein the wherein the stepped slot in the memory module connector is configured so that at least one of the plurality of components mounted on the printed circuit board is positioned in the stepped slot. Other embodiments are described and claimed.

Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

Abstract: In one embodiment, an apparatus comprises a first connector to couple to a connector of a memory card, the memory card comprising a first sense node to sense a supply voltage at a first location of the memory card, the first connector comprising a voltage supply pin; a ground pin; and a sense pin to couple to the first sense node; a first sense line to couple to the first sense node through the sense pin; and a voltage regulator coupled to the first sense line, the voltage regulator to provide the supply voltage based on feedback received from the first sense node of the memory card via the first sense line.

Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.