Patents by Inventor Georges Thomas

Georges Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10362978
    Abstract: According to some aspects, disclosed methods and systems may include having a user input one or more speech commands into an input device of a user device. The user device may communicate with one or more components or devices at a local office or headend. The local office or the user device may transcribe the speech commands into language transcriptions. The local office or the user device may determine a mood for the user based on whether any of the speech commands may have been repeated. The local office or the user device may determine, based on the mood of the user, which content asset or content service to make available to the user device.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 30, 2019
    Assignee: Comcast Cable Communications, LLC
    Inventors: George Thomas Des Jardins, Scot Zola, Vikrant Sagar
  • Patent number: 10360924
    Abstract: A system for removing noise from an audio signal is described. For example, noise caused by content playing in the background during a voice command or phone call may be removed from the audio signal representing the voice command or phone call. By removing noise, the signal to noise ratio of the audio signal may be improved.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: July 23, 2019
    Assignee: Comcast Cable Communications, LLC
    Inventor: George Thomas Des Jardins
  • Patent number: 10353815
    Abstract: The disclosed technology is generally directed to data security. In one example of the technology, data is stored in a memory. The memory includes a plurality of memory banks including a first memory bank and a second memory bank. At least a portion of the data is interleaved amongst at least two of the plurality of memory banks. Access is caused to be prevented to at least one of the plurality of memory banks while a debug mode or recovery mode is occurring. Also, access is caused to be prevented to the at least one of the plurality of memory banks starting with initial boot until a verification by a security complex is successful. The verification by the security complex includes the security complex verifying a signature.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 16, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: George Thomas Letey, Douglas L. Stiles, Edmund B. Nightingale
  • Patent number: 10346345
    Abstract: The disclosed technology is generally directed to peripheral access. In one example of the technology, stored configuration information is read. The stored configuration information is associated with mapping a plurality of independent execution environments to a plurality of peripherals such that the peripherals of the plurality of peripherals have corresponding independent execution environments of the plurality of independent execution environments. A configurable interrupt routing table is programmed based on the configuration information. An interrupt is received from a peripheral. The interrupt is routed to the corresponding independent execution environment based on the configurable interrupt routing table.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 9, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: George Thomas Letey, Douglas L. Stiles, Edmund B. Nightingale
  • Patent number: 10344380
    Abstract: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: July 9, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Arash Abedijaberi, Shawn George Thomas
  • Patent number: 10332782
    Abstract: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 25, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Shawn George Thomas
  • Publication number: 20190181036
    Abstract: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.
    Type: Application
    Filed: May 18, 2016
    Publication date: June 13, 2019
    Inventors: Gang Wang, Shawn George Thomas
  • Patent number: 10320259
    Abstract: A method of manufacturing a motor, which begins with robotically positioning a flexible insulating sleeve over a first motor sub-assembly to produce a second motor sub-assembly. The first motor sub-assembly includes a motor assembly and an end-cap. The motor assembly includes a stator, a rotor, and wiring connected to the stator. The end-cap includes an electrical fitting for feeding the wiring externally of the motor. The method continues with robotically positioning a flexible enclosure, that includes a formed housing section and a connecting section, loosely over the second motor sub-assembly. The method continues with tightening the connecting section until the formed housing section tightly fits over the second sub-assembly compressing the flexible insulating sleeve to produce an insulating seal.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 11, 2019
    Assignee: Bison Gear & Engineering Corp.
    Inventors: Matthew Sherman Hanson, George Thomas, Gary Dorough, Jeff Hamaker, Edmund Peter Henke, Jr., Sanel Tatar
  • Patent number: 10304722
    Abstract: The disclosed method is suitable for producing a semiconductor-on-insulator structure, such as a Ge(Si)-on-insulator structure or a Ge-on-insulator structure. According to the method, a multilayer comprising alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer. The multilayer is completed with a silicon passivation layer. A cleave plane is formed within the multilayer, and the multilayer structure is bonded to a handle substrate comprising a dielectric layer. The multilayer structure is cleaved along the cleave plane to thereby prepare a semiconductor-on-insulator structure comprising a semiconductor handle substrate, a dielectric layer, a silicon passivation layer, and at least a portion of the alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 28, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Shawn George Thomas
  • Publication number: 20190142835
    Abstract: Provided are methods and pharmaceutical combinations utilizing a phospholipase A2 inhibitor for the inhibition of treatment-induced autophagy.
    Type: Application
    Filed: November 14, 2018
    Publication date: May 16, 2019
    Applicant: OREGON HEALTH & SCIENCE UNIVERSITY
    Inventors: George Thomas, Jennifer Podolak, Hui-wen Lue, Kevin Kolahi
  • Publication number: 20190149119
    Abstract: Systems and methods for adjusting impedances or power or a combination thereof across multiple plasma processing stations are described. One of the systems includes a first radio frequency (RF) generator that generates a first RF signal having a first frequency, a second RF generator that generates a second RF signal having a second frequency, and a first matching network coupled to the first RF generator to receive the first RF signal. The first impedance matching network outputs a first modified RF signal upon receiving the first RF signal. The system further includes a second matching network coupled to the second RF generator to receive the second RF signal. The second matching network outputs a second modified RF signal upon receiving the second RF signal. The system further includes a combiner and distributor coupled to an output of the first matching network and an output of the second matching network.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Inventors: Sunil Kapoor, George Thomas, Yaswanth Rangineni, Edward Augustyniak
  • Publication number: 20190136376
    Abstract: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Arash Abedijaberi, Shawn George Thomas
  • Publication number: 20190136375
    Abstract: A liner assembly for a substrate processing system includes a first liner and a second liner. The first liner includes an annular body and an outer peripheral surface including a first fluid guide. The first fluid guide is curved about a circumferential line extending around the first liner. The second liner includes an annular body, an outer rim, an inner rim, a second fluid guide extending between the outer rim and the inner rim, and a plurality of partition walls extending outwardly from the second fluid guide. The second fluid guide is curved about the circumferential line when the first and second liners are positioned within the processing system.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Arash Abedijaberi, Shawn George Thomas
  • Publication number: 20190139818
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 10283402
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 7, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Igor Peidous
  • Patent number: 10253028
    Abstract: The compound 3,3,3-trifluoro-N-((1,4-trans)-4-((3-((S)-2-methylmorpholino)-IH-pyrazolo[3,4-d]pyrimidin-6-yl)amino)cyclohexyl)propane-1-sulfonamide having the Formula (I) or a salt thereof, its opposite enantiomer, compositions comprising the compound and its use in the treatment or prevention of leishmaniasis, particularly visceral leishmaniasis.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: April 9, 2019
    Assignees: GlaxoSmithKline Intellectual Property Development Limited, University of Dundee
    Inventors: Timothy James Miles, Michael George Thomas
  • Publication number: 20190096745
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 28, 2019
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Igor Peidous
  • Publication number: 20190089771
    Abstract: Embodiments of the systems described herein can implement one or more processes remotely delivering customized code to a host application and/or computing device. The host application may be configured as an Application Programming Interface with a customized code processing library that may configure the host application to receive further instructions remotely. The host application may be further configured to execute host code and/or third-party code. The host application may be configured to receive remote application logic, after the host application has been installed on a computing device, and to execute the received application logic to alter the behavior of the host application, such as selectively tracking end user interactions.
    Type: Application
    Filed: June 15, 2018
    Publication date: March 21, 2019
    Inventors: Patrick McWilliams, Jason Lap-Wing Koo, Chad Major Hartman, George Thomas Webster, IV, Son Phi Hoang
  • Patent number: 10187743
    Abstract: Systems, methods, and other embodiments are disclosed that provide situation awareness to a user of a mobile computing device. In one embodiment, beacon data is received by the mobile computing device, indicating beacon devices that are within reception range of the mobile computing device within an environment. The mobile computing device accesses local map data and local asset data based on a current location and a user of the mobile computing device. The current location is based on the beacon data and the user is defined by user profile data. The mobile computing device determines a display map and asset icons based on the local map data, the local asset data, and the user profile data. The asset icons are displayed overlaid on the display map on a display screen of the mobile computing device.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 22, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: George Thomas, Yue Zhou
  • Patent number: 10187032
    Abstract: Systems and methods for adjusting impedances or power or a combination thereof across multiple plasma processing stations are described. One of the systems includes a first radio frequency (RF) generator that generates a first RF signal having a first frequency, a second RF generator that generates a second RF signal having a second frequency, and a first matching network coupled to the first RF generator to receive the first RF signal. The first impedance matching network outputs a first modified RF signal upon receiving the first RF signal. The system further includes a second matching network coupled to the second RF generator to receive the second RF signal. The second matching network outputs a second modified RF signal upon receiving the second RF signal. The system further includes a combiner and distributor coupled to an output of the first matching network and an output of the second matching network.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: January 22, 2019
    Assignee: Lam Research Corporation
    Inventors: Sunil Kapoor, George Thomas, Yaswanth Rangineni, Edward Augustyniak