Patents by Inventor Georges Thomas

Georges Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10170955
    Abstract: A motor includes a motor assembly, an end cap, a flexible insulating sleeve, and a flexible enclosure. The motor assembly includes a stator, a rotor, and wiring connected to the stator. The end-cap is coupled to the motor assembly to produce first sub-assembly. In addition, the end-cap includes an electrical fitting for feeding the wiring externally of the motor. The flexible insulating sleeve fits over at a least a portion the first sub-assembly to produce a second sub-assembly. The flexible enclosure includes a formed housing section and a connecting section. The formed housing section loosely fits over the second sub-assembly prior to tightening of the connecting section and, when the connecting section is tightened, the formed housing section tightly fits over the second sub-assembly compressing the flexible insulating sleeve to produce an insulating seal.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: January 1, 2019
    Assignee: BISON GEAR & ENGINEERING CORP.
    Inventors: Matthew Sherman Hanson, George Thomas, Gary Dorough, Jeff Hamaker, Edmund Peter Henke, Jr., Sanel Tatar
  • Publication number: 20180348347
    Abstract: A scanning display system includes two detectors for rangefinding. Round trip times-of-flight are measured for reflections of laser pulses received at the detectors. A proportional correction factor is determined based at least in part on the geometry of the scanning display system. The proportional correction factor is applied to the measured times-of-flight to create estimates of more accurate times-of-flight.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 6, 2018
    Inventors: Bin Xue, P. Selvan Viswanathan, Robert James Jackson, George Thomas Valliath
  • Publication number: 20180350661
    Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 6, 2018
    Inventors: Igor Peidous, Srikanth Kommu, Gang Wang, Shawn George Thomas
  • Patent number: 10145011
    Abstract: A system for depositing a layer on a substrate includes a processing chamber including a gas inlet, a plurality of gas flow controllers connected in fluid communication with a gas supply source, a gas distribution plate disposed between the plurality of gas flow controllers and the gas inlet, and a gas injection cap connected in fluid communication between the plurality of gas flow controllers and the gas distribution plate. The gas distribution plate defines a plurality of holes, and the gas injection cap defines a plurality of gas flow passages, each extending from an inlet connected to one of the gas flow controllers to an outlet connected in fluid communication with at least one of the holes in the gas distribution plate. Each of the gas flow controllers is disposed proximate to the gas injection cap.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 4, 2018
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Arash Abedijaberi, John A. Pitney, Shawn George Thomas
  • Publication number: 20180341584
    Abstract: The disclosed technology is generally directed to data security. In one example of the technology, data is stored in a memory. The memory includes a plurality of memory banks including a first memory bank and a second memory bank. At least a portion of the data is interleaved amongst at least two of the plurality of memory banks. Access is caused to be prevented to at least one of the plurality of memory banks while a debug mode or recovery mode is occurring. Also, access is caused to be prevented to the at least one of the plurality of memory banks starting with initial boot until a verification by a security complex is successful. The verification by the security complex includes the security complex verifying a signature.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Inventors: George Thomas LETEY, Douglas L. STILES, Edmund B. NIGHTINGALE
  • Publication number: 20180341620
    Abstract: The disclosed technology is generally directed to peripheral access. In one example of the technology, stored configuration information is read. The stored configuration information is associated with mapping a plurality of independent execution environments to a plurality of peripherals such that the peripherals of the plurality of peripherals have corresponding independent execution environments of the plurality of independent execution environments. A configurable interrupt routing table is programmed based on the configuration information. An interrupt is received from a peripheral. The interrupt is routed to the corresponding independent execution environment based on the configurable interrupt routing table.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Inventors: George Thomas LETEY, Douglas L. STILES, Edmund B. NIGHTINGALE
  • Publication number: 20180343234
    Abstract: The disclosed technology is generally directed to firewalls. In one example of the technology, a first firewall is used such that communication is blocked from a first subsystem of a device upon boot of the device. The first firewall is enabled to be configured by secure code subsequent to boot such that code that is not secure code is prevented from configuring the first firewall. After configuration of the first firewall, based on the configuration, the first firewall is used to selectively allow the first subsystem access to the first memory based on ranges of addresses of the first memory configured as accessible to the first subsystem.
    Type: Application
    Filed: May 26, 2017
    Publication date: November 29, 2018
    Inventors: George Thomas LETEY, Douglas L. STILES, Edmund B. NIGHTINGALE
  • Publication number: 20180313744
    Abstract: The present invention is directed to system and process for corrosion monitoring. An embodiment of a system includes a conductor, an electrical connector, a sensor system, a transmitter, a network, and a computer having a database. The conductor is one or more current carrying conductors inline with and having a connector at each end such that there is electrical communication from connector to connector. The sensor system is configured for attachment to the conductor, and is operable to measure one or more of resistance, temperature, current flow, surrounding radio frequency and/or magnetic flux. The transmitter coupled the sensor system, operable to transmit data from the sensor system over a network to a processor for further processing. The computer includes a database for storage of sensor system in the form of instantaneous values, average values, a series of values, vectors representing values, or waveforms.
    Type: Application
    Filed: April 18, 2018
    Publication date: November 1, 2018
    Inventors: George Thomas Hazelton, JR., Yehyun Choi, Woochan Kim, Daewook Kwon, Tae-Hyeon Kim
  • Publication number: 20180294183
    Abstract: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.
    Type: Application
    Filed: May 18, 2016
    Publication date: October 11, 2018
    Inventors: Gang Wang, Shawn George Thomas
  • Publication number: 20180294182
    Abstract: The disclosed method is suitable for producing a semiconductor-on-insulator structure, such as a Ge(Si)-on-insulator structure or a Ge-on-insulator structure. According to the method, a multilayer comprising alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer. The multilayer is completed with a silicon passivation layer. A cleave plane is formed within the multilayer, and the multilayer structure is bonded to a handle substrate comprising a dielectric layer. The multilayer structure is cleaved along the cleave plane to thereby prepare a semiconductor-on-insulator structure comprising a semiconductor handle substrate, a dielectric layer, a silicon passivation layer, and at least a portion of the alternating pairs of layers, comprising a layer of silicon and a layer of germanium option ally with silicon.
    Type: Application
    Filed: May 23, 2016
    Publication date: October 11, 2018
    Inventors: Gang Wang, Shawn George Thomas
  • Publication number: 20180282865
    Abstract: A preheat ring (126) for use in a chemical vapor deposition system includes a first portion and a second portion selectively coupled to the first portion such that the first and second portions combine to form an opening configured to receive a susceptor therein. Each of the first and second portions is independently moveable with respect to each other.
    Type: Application
    Filed: September 29, 2016
    Publication date: October 4, 2018
    Inventors: Gang Wang, Shawn George Thomas
  • Publication number: 20180274862
    Abstract: A support ring for supporting a semiconductor wafer in a boat of a vertical furnace used in processing of the semiconductor wafer includes a semicircular segment. The semicircular segment has an upper surface, a lower surface opposite the upper surface, a radial inner wall defining an inner radius, and a radial outer wall defining an outer radius. The support ring further includes protrusions in the upper surface of the semicircular segment. The protrusions extend above the upper surface.
    Type: Application
    Filed: June 1, 2018
    Publication date: September 27, 2018
    Inventors: Qingmin Liu, William Lynn Luter, Shawn George Thomas
  • Patent number: 10079170
    Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA- nitrides, semiconductor oxides, and any combination thereof.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: September 18, 2018
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Srikanth Kommu, Gang Wang, Shawn George Thomas
  • Patent number: 10072892
    Abstract: A support ring for supporting a semiconductor wafer in a boat of a vertical furnace used in processing of the semiconductor wafer includes a semicircular segment. The semicircular segment has an upper surface, a lower surface opposite the upper surface, a radial inner wall defining an inner radius, and a radial outer wall defining an outer radius. The support ring further includes protrusions in the upper surface of the semicircular segment. The protrusions extend above the upper surface.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: September 11, 2018
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Qingmin Liu, William Lynn Luter, Shawn George Thomas
  • Patent number: 10065965
    Abstract: A compound of Formula (I), or a salt thereof, compositions comprising the compound, processes for its preparation and its use in therapy, for example in the treatment of parasitic diseases such as Chagas disease, Human African Trypanosomiasis (HAT) and leishmaniasis, particularly visceral leishmaniasis (VL).
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 4, 2018
    Assignees: GlaxoSmithKline Intellectual Property Development Limited, The University of Dundee
    Inventors: Stephen Brand, Elisabet Viayna Gaza, Ian Gilbert, Eun Jung Ko, Maria Marco Martin, Timothy James Miles, Lars Henrik Sandberg, Michael George Thomas
  • Publication number: 20180233400
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 16, 2018
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Igor Peidous
  • Publication number: 20180222911
    Abstract: A compound of Formula (I), or a salt thereof, compositions comprising the compound, processes for its preparation and its use in therapy, for example in the treatment of parasitic diseases such as Chagas disease, Human African Trypanosomiasis (HAT), Animal African trypanosomiasis (AAT) and leishmaniasis, particularly visceral leishmaniasis (VL).
    Type: Application
    Filed: August 3, 2016
    Publication date: August 9, 2018
    Inventors: Stephen BRAND, Peter George DODD, Eun Jung KO, Maria MARCO MARTIN, Timothy James MILES, Lars Henrik SANDBERG, Michael George THOMAS, Stephen THOMPSON
  • Publication number: 20180190312
    Abstract: A system for removing noise from an audio signal is described. For example, noise caused by content playing in the background during a voice command or phone call may be removed from the audio signal representing the voice command or phone call. By removing noise, the signal to noise ratio of the audio signal may be improved.
    Type: Application
    Filed: August 17, 2017
    Publication date: July 5, 2018
    Applicants: Comcast Cable Communications, LLC, Comcast Cable Communications, LLC
    Inventor: George Thomas Des Jardins, Jardins
  • Patent number: 10003639
    Abstract: Embodiments of the systems described herein can implement one or more processes remotely delivering customized code to a host application and/or computing device. The host application may be configured as an Application Programming Interface with a customized code processing library that may configure the host application to receive further instructions remotely. The host application may be further configured to execute host code and/or third-party code. The host application may be configured to receive remote application logic, after the host application has been installed on a computing device, and to execute the received application logic to alter the behavior of the host application, such as selectively tracking end user interactions.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 19, 2018
    Assignee: TEALIUM INC.
    Inventors: Patrick McWilliams, Jason Lap-Wing Koo, Chad Major Hartman, George Thomas Webster, IV, Son Phi Hoang
  • Publication number: 20180165448
    Abstract: The disclosed technology is generally directed to integrated circuit technology with defense-in-depth. In one example of the technology, an integrated circuit includes a set of independent execution environments including at least two independent execution environments. At least two of the independent execution environments are general purpose cores with differing capabilities. The independent execution environments in the set of independent execution environments are configured to have a defense-in-depth hierarchy.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 14, 2018
    Inventors: Edmund B. Nightingale, Reuben R. Olinsky, Galen C. Hunt, Douglas Stiles, George Thomas Letey