Abstract: A method that enables an optical transceiver (or optical transmitter or optical receiver) to perform consistency checking such as Cyclic Redundancy Checking (CRC) in the background while the transceiver is in operation. The optical transceiver includes a system memory and a consistency checker component. The optical transceiver determines that consistency checking is to be performed and identifies non-contiguous static portions of the system memory to be checked. The consistency checker reads the non-contiguous static portions of system memory and determines whether or not the portions of system memory are consistent with an expected consistency check value.

Abstract: An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver.

Abstract: An operational optical transceiver configured to preserve a portion of volatile memory during a warm reboot process. The optical transceiver includes a persistent memory, a processor, and a system memory. The system memory includes a preserved memory space. The optical transceiver loads microcode from the persistent memory to the system memory without writing into the preserved memory space. The processor processes the microcode and writes certain information into the preserved memory space that will be preserved during a warm reboot. The optical transceiver may then initiate a warm reboot and load microcode from the persistent memory to the system memory that overwrites the existing microcode. However, the information written in the preserved memory space is not overwritten by the microcode loaded from the persistent memory. In this way, a portion of the information contained in the system memory prior to the warm reboot is preserved.

Abstract: A method for changing the host communication interface address for a number of individual optical transceivers sharing a single host communication interface. An optical transceiver host computing system is communicatively coupled to the transceivers using the single host communication interface. The host computing system implements the host interface address change by indicating to a first transceiver that an address change is pending. The host then informs the first transceiver that it is to have its address changed using a mechanism independent of the addressing mechanism used by the signal host communication interface. In response, the first transceiver makes the address change. The other optical transceivers may have their address changed using the same method, although this is not required.

Abstract: An operational optical transceiver configured to dynamically adjust the boot speed of the optical transceiver boot process. The optical transceiver includes a persistent memory, a system memory, and a controller configured to load information from the persistent memory to the system memory. The controller initiates the boot process at a slower boot speed and begins to load information from the persistent memory to the system memory. The controller then detects boot speed data in the information being loaded to the system memory that defines a faster boot speed. In response to the detected boot speed data, the controller continues the boot process by loading additional information from the persistent memory to the system memory at a second boot speed that is faster than the first boot speed.

Abstract: An optical transceiver (or transmitter or receiver) that uses microcode and an internal sensor to self-calibrate itself to an environmental parameter such as, for example, temperature. In particular, the optical transceiver senses the environmental parameter under changing environmental circumstances. The optical transceiver then calculates how an operational parameter such as laser bias current should change based on the sensing operation. The optical transceiver then persistently records an approximation of the relation between the environmental parameter and the operational parameter. This approximation may later be used during operation to adjust the operational parameter as appropriate given then-existing environmental circumstances.

Abstract: A method for dynamically updating an optical transceiver (or optical transmitter or optical receiver) that has at least one processor and persistent memory that includes one or more write-protected memory locations. The write-protected memory locations of the persistent memory includes loader microcode that, when executed by the at least one processor, causes the optical transceiver to have access to a first set of functionality. In order to implement the invention, the optical transceiver first processes received microcode. Then, the processed representation of the received microcode is written to the persistent memory outside of the one or more write-protected memory locations. The optical transceiver then determines that all of the microcode that is to be written to the persistent memory during the update has been written to the persistent memory. Finally, the persistent memory is altered to reflect that the update is complete.

Abstract: Systems and methods for an optical transceiver module to limit the amount of time the optical transceiver module is allowed to operate. The optical transceiver module includes at least one processor, a persistent memory and a system memory. The persistent memory, which is coupled to the at least one processor, contains microcode. The microcode is loaded from the persistent memory to the system memory and executed by the at least one processor. The executed microcode causes the optical transceiver module to detect the amount of time that the optical transceiver has been operating. The optical transceiver module then determines if the detected amount of operating time is in excess of a predetermined amount of operating time. If the detected operating time is in excess of the predetermined amount of operating time, the optical transceiver module causes itself to become non-operational. The optical transceiver module may then report its operational status.

Abstract: An optical transceiver configured to transmit and receive optical signals. The optical transceiver includes a control module and a persistent memory. The control module is configured to identify operational information regarding the optical transceiver, and write log information representing the operational information to the persistent memory. The operation information may include statistical data about operation, or may include measured parameters. Log entries may be made periodically and/or in response to events. The log may then be evaluated to determine the conditions under which the transceiver has historically operated.

Abstract: Systems and methods for an optical transceiver module to perform one or more diagnostic self-tests without the assistance of a host computing system. The optical transceiver module includes at least one processor, a persistent memory and a system memory. The persistent memory, which is coupled to the at least one processor, contains microcode. The microcode is loaded from the persistent memory to the system memory and executed by the at least one processor. The executed microcode causes the optical transceiver module to perform one or more diagnostic self-tests. The diagnostic result data of the one or more diagnostic self-tests is then stored in the persistent memory and is formatted for analysis. The formatted data may then be analyzed to ascertain the response of the optical transceiver to changes in its test environment.

Abstract: Watchdog instructions embedded within the actual microcode that is executed by the processor. Accordingly, as the processor reads and executes the microcode, the processor occasionally encounters the watchdog instruction. Each time the processor executes the watchdog instruction, the processor generates a watchdog signal. A watchdog signal detection circuit detects the presence of the periodic signal. If the watchdog signal has not occurred when expected, then some instability has likely occurred. Accordingly, the watchdog signal detection circuit causes some corrective action to be taken when a watchdog signal is not detected when expected. Such corrective action may include, for example, rebooting the system or resetting one or more modules of the system. The inclusion of the watchdog instruction within the microcode increases the chance that the watchdog signal will be an accurate predictor of system stability.

Abstract: A microcode-initiated high speed comparator in an optical transceiver includes an initialization and control section consisting of various register sets, an analog section with comparator hardware, and an output retrieval section. The comparator hardware performs comparison on a wide-range of selectable input values, thereby avoiding the need for a dedicated comparator for each input value. The register sets are initialized by microcode with various comparison values, allowing multiplexed comparison to be much faster than it would be if the processor was controlling in real-time the multiplexed comparison. The comparison values may correspond to optimal operational parameters of the optical transceiver or may correspond to other desired comparison values. The analog section is driven by the registers and makes a comparison between the predetermined values and actual operational parameter values.

Abstract: An optical transceiver configured to perform calibration of digital diagnostics prior to providing the calibrated values to a host computing system (hereinafter referred to simply as a “host”) that is communicatively coupled to the optical transceiver. The optical transceiver includes a sensor that measures an analog operational parameter signal such as temperature or supply voltage. Each analog signal is then converted to digital samples by analog to digital converter(s). A processor executes microcode that causes the optical transceiver to perform calibration on the various samples to compensate for predictable error introduced into the analog signal prior to or during the analog-to-digital conversion. The optical transceiver may then make the calibrated result accessible to the host.

Abstract: A telecommunications system and constituent integrated circuit that includes a post-amplifier assembly configured for communication with an optical receiver, a laser driver assembly configured for communication with the optical transmitter, and a controller assembly configured to control the post-amplifier and laser driver. The post-amplifier, the laser driver, and the controller assemblies are embodied on a single integrated circuit, thereby reducing manufacturing costs. Noise due to clock generation may be reduced by having the clock act on a transient basis, turning on when needed during the boot process, and turning off when not needed during normal operation.

Abstract: Configuring chip I/O terminals such that they may be input, output, or bi-directional terminals. Furthermore, the I/O terminals may be configured with different signal sources if they are output or bi-directional terminals. In addition, the terminals may be configured to be inverted when operating in either direction. A mechanism is provided to change this configuration as needed, for example, to correspond to different pins on the package as appropriate given the package configuration and other implementation needs. This configurability allows for tremendous flexibility and independent between the chip on which the integrated circuit is embedded and the package.

Abstract: Mechanisms for performing per-bit operations in system memory in a single operation thereby obviating the need for semaphore mechanisms when performing per-bit operations. A processor accesses an instruction that identifies the specific bit of system memory that is to be operated upon, as well as an operation to be performed on the bit. The operation may be, for example, a bit set, clear, or toggle. The processor then instructs system memory to perform the operation. Since the operation is performed in a single operation, other processes do not need to wait before continuing operation on the memory address of the specific bit. In addition, semaphores restricting access to the memory address need not be used while still retaining adequate assurance that the memory address will remain consistent.

Abstract: An architecture and method in an integrated circuit for configuring a controller to facilitate communication with a plurality of external device interfaces. The integrated circuit includes a processor, a first memory, a second memory, including a plurality of dedicated memory blocks containing configuration data, and a plurality of external device interfaces. The processor is configured to write a microcode instruction to the first memory. The controller is configured to read the microcode instruction in the first memory and as a result access one of the plurality of dedicated memory blocks. Next, the controller processes the configuration data in the dedicated memory block according to the microcode instruction. As a result, the controller is configured to communicate with one of the plurality of external device interfaces. This process may be repeated as needed to configure the controller to communicate with different device interfaces using different communication protocols.

Abstract: Mechanisms for configuring an integrated circuit to select one of multiple external device interfaces at a time to use during communication with external devices. The integrated circuit includes a control mechanism, a selection mechanism, and a plurality of external device interfaces. The plurality of device interfaces allow the integrated circuit to communicate with various external devices that support different communication protocols. The control mechanism is configured to designate the selection of one of the plurality of device interfaces for use in communicating with an external device. The control mechanism makes use of the selection mechanism to select the designated device interface to communicate with using the communication protocol supported by the selected interface. The communication may be receiving data from the interface or providing data to the interface. Non-selected interfaces are put in an inactive state.

Abstract: A telecommunications system that includes an external memory, an internal memory and a system clock. A boot component is configured to use the clock signal generated by the system clock to load data from external memory into internal memory when the telecommunication system operates in initialization mode. The telecommunication system is configured to operate based on the loaded data in internal memory when the system operates in normal mode. Once the initialization mode is complete, the system clock may be shut down since the telecommunication system does not need the system clock to perform normal mode operations. Subsequently, the system clock may be restarted if need be. Accordingly, the system clock is generated when it is needed, but not continuously. Therefore, cross-talk between the system clock and the receive and transmit path is reduced.

Abstract: An operational optical transceiver comprising a receiver, a sensor, a memory, and a processor. The sensor is configured to measure the received power of an optical signal received by the receiver. The received power is sent to the memory where it is read by the processor. The processor is configured by microcode stored in the memory to compare the measured power value with a threshold power value. If the measured power value is below the threshold, then the transceiver will assert an indicator such as a signal indicating this. At a later time, when the measured power level is again above the threshold value, the transceiver will deassert the indicator previously asserted.