Abstract: Circuitry for monitoring the operation of an optoelectronic transceiver includes a sequence of interconnected signal processing circuits for processing an analog input signal and producing a digital result signal, where the analog signal represents one or more operating conditions of the optoelectronic transceiver. The sequence of signal processing circuits include gain circuitry for amplifying or attenuating the analog input signal by a gain value to produce a scaled analog signal, an analog to digital converter for converting the scaled analog signal into a first digital signal, and digital adjustment circuitry for digitally adjusting the first digital signal to produce the digital result signal. The digital adjustment circuitry includes shifting circuitry configured to shift an input digital signal in accordance with a shift value so as to produce a digital shifted signal. The digital result signal is stored in memory in predefined locations accessible by a host.

Abstract: A circuit module having one of more digital input terminals that are capable of receiving a third input state to initiate non-standard operational modes such as might be desired during programming or testing of the module or its surrounding circuitry. For each of these special digital input terminals, there is a component that recognizes the presence of the third state applied to the corresponding input terminal. In response, the component generates a signal that causes the module to enter the non-standard operational mode. A non-standard operational mode is a mode other than the normal operational mode of the module. As an example, the non-standard operational mode might be a testing or programming mode that is encountered prior to even shipping the module to a consumer.

Abstract: A guaranteed two-wire interface in which upon determining that an operation is to be performed on a slave component, a master component transmits at least a portion of a corresponding frame to the slave component over the data wire. The master component repeats this detection and transmission each time it determines that an operation is to be performed on a slave component, whether the same component or a different slave component as the slave component previously communicated with. The frame structure itself may change depending on the operation to be performed. For example, one frame might include an extended address data field that includes extended address information that goes beyond a basic address field included in another frame. One frame may include reliability fields (such as cyclic redundancy checking field, an acknowledgement field, and/or an error field), whereas another frame having a different operation may not.

Abstract: Systems and methods for verifying that an optical transceiver has access privileges to received microcode. An example environment may include an optical transceiver that is coupled to a host computing system. The optical transceiver includes a memory that has thereon an optical transceiver access identifier. The optical transceiver memory is also configured to receive microcode that includes a microcode access identifier. Whenever new microcode is received by the optical transceiver, it is verified whether the optical transceiver should have access privileges to the microcode. To verify that the optical transceiver has access privileges, the optical transceiver access identifier and the microcode access identifier are accessed. The accessed identifiers are then compared with one another. Based on the comparison, the received microcode is loaded into the memory if one or more portions of the access identifiers match.

Abstract: A guaranteed two-wire interface in which upon determining that an operation is to be performed on a slave component, the master component begins transmitting the frame to the slave component including an identification of the operation to be performed. The master component then transfers control of the data wire to the slave component. The slave component then transmits a remaining portion of the frame to the master component over the data wire. The frame includes reliability information such as cyclic redundancy checking data or acknowledgement data that the master component may then use to determine whether the operation was successful.

Abstract: Microcode driven adjustment of analog scaling of an analog signal prior to being provided to an analog-to-digital converter. The microcode also causes the system to read the resulting digital value, and determine whether the scaling value should be adjusted for that analog signal. Accordingly, the microcode may cause the analog signal to be dynamically adjusted to be within the input range of the analog-to-digital converter, thereby allowing for more accurate digital conversions with lower resolution analog-to-digital converters. The microcode rapidly adjusts for any fluctuations in the input voltage. Accordingly, the analog signal may fluctuate, or even be multiplexed from a wide variety of different analog signal sources.