Abstract: A detector module comprises: a direct conversion crystal for converting incident photons into electrical signals, the direct conversion crystal having an anode layer deposited on a first surface and a cathode layer deposited on a second surface; a redistribution layer deposited on the anode layer, the redistribution layer configured to adapt a pad array layout of the direct conversion crystal to a predetermined lead pattern; an integrated circuit in electrical communication with the direct conversion crystal; and a plurality of input/output electrical paths connected to the redistribution layer to provide connectivity between the imaging module and another level of interconnect.

Abstract: An electrical switching device includes a housing, a base attached to the housing, two non-actuated electrical contacts supported in the housing, and an actuator assembly contained within the housing. The actuator assembly includes a movable contact for engaging the non-actuated electrical contact and a wire element formed of a shape memory alloy. Applying an electric current to the wire element causes the actuator to either pivot or rotate the movable contact to either engage or disengage the non-actuated electrical contacts.

Abstract: An ultrasound probe includes a transducer comprising an array of transducer elements removably disposed in a head portion. At least one or more stages of electronic circuit units is removably coupled to the transducer and configured to excite the transducer. A handle portion is detachably coupled to the head portion. The head portion and the handle portion are disposed enclosing the at least one or more stages of electronic circuit units. The ultrasound probe is used for one dimensional applications, two dimensional applications, and volumetric applications.

Abstract: A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.

Abstract: A cooling device includes a ceramic substrate with a metal layer bonded to an outer planar surface. The cooling device also includes a channel layer bonded to an opposite side of the ceramic substrate and a manifold layer bonded to an outer surface of the channel layer. The substrate layers are bonded together using a high temperature process such as brazing to form a single substrate assembly. A plenum housing is bonded to the single substrate assembly via a low temperature bonding process such as adhesive bonding and is configured to provide extended manifold layer inlet and outlet ports.

Abstract: A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.

Abstract: An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a sur

Abstract: An electronic component includes a base insulative layer having a first surface and a second surface; an electronic device having a first surface and a second surface, and the electronic device being secured to the base insulative layer; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer. The base insulative layer secures to the electronic device through the removable layer. The removable layer is capable of releasing the base insulative layer from the electronic device. The removal may be done without damage to a predetermined part of the electronic component.

Abstract: A method for making an interconnect structure includes applying a first metal layer to an electronic device, wherein the electronic device comprises at least one I/O contact and the first metal layer is located on a surface of the I/O contact; applying a removable layer to the electronic device. The removable layer is adjacent to the first metal layer. An adhesive layer is applied to the electronic device or to a base insulative layer. The electronic device is secured to the base insulative layer using the adhesive layer. The first metal layer and removable layer are disposed between the electronic device and the base insulative layer.

Abstract: An electronic component includes a base insulative layer having a first surface and a second surface; an electronic device having a first surface and a second surface; at least one I/O contact located on the first surface of the electronic device; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; a first metal layer disposed on the I/O contact; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer, and located adjacent to the first metal layer. The base insulative layer secures to the electronic device through the first metal layer and removable layer, wherein the first metal layer and removable layer are capable of releasing the base insulative layer from the electronic device when the first metal layer and removable layer are exposed to a temperature higher than their softening points or melting points.

Abstract: A method is provided for making an interconnect structure. The method includes applying a removable layer to an electronic device or to a base insulative layer; applying an adhesive layer to the electronic device or to the base insulative layer; and securing the electronic device to the base insulative layer using the adhesive layer.

Abstract: An ultrasound monitoring system. In one embodiment, an array of transducer cells is formed along a first plane and an integrated circuit structure, formed along a second plane parallel to the first plane, includes an array of circuit cells. A connector provides electrical connections between the array of transducer cells and the array of circuit cells, and an interconnection structure is connected to transfer signals between the circuit cells and processing and control circuitry. The integrated circuit structure includes a semiconductor substrate and a plurality of conductive through-die vias formed through the substrate to provide Input/Output (I/O) connections between the transducer cells and the interconnection structure. The monitoring system may be configured as an imaging system and the processing and control circuitry may be external to the probe unit.

Abstract: The present invention relates to a method for making an integrated sensor comprising providing a sensor array fabricated on a top surface of a bulk silicon wafer having a top surface and a bottom surface, and comprising a plurality of sensors fabricated on the top surface of the bulk silicon wafer. The method further comprises coupling an SOI wafer to the top surface of the bulk silicon wafer, thinning the back surface of the bulk silicon wafer, coupling a plurality of integrated circuit die to the back surface of the bulk silicon wafer, and removing the SOI wafer from the top surface of the bulk silicon wafer.

Abstract: A modular sensor assembly and methods of fabricating a modular sensor assembly are provided. The modular sensor assembly includes a sensor array coupled to an electronics array in a stacked configuration. The sensor array comprises a plurality of sensor modules, each comprising a plurality of sensor sub-arrays. The electronics array comprises a plurality of integrated circuit modules, each comprising a plurality of integrated circuit chips. The sensor modules may be coupled to the electronics modules via flip chip technology.

Abstract: An ultrasonic monitoring system is formed with a probe unit. In one example an array of transducer cells is arranged in rows and columns formed along a first plane with a first pitch along a first direction. An integrated circuit including an array of circuit cells is formed along a second plane parallel to the first plane. The circuit cells are spaced apart along the first direction at a second pitch smaller than the first pitch. A first of the transducer cells is vertically aligned, along a direction normal to one of the planes, with a first of the circuit cells and having a connection thereto. A second of the transducer cells is offset from vertical alignment with respect to the position of a second circuit cell so as to not overlie the second circuit cell.

Abstract: A modular sensor assembly and methods of fabricating a modular sensor assembly are provided. The modular sensor assembly includes a sensor array coupled to an electronics array in a stacked configuration. The sensor array comprises a plurality of sensor modules, each comprising a plurality of sensor sub-arrays. The electronics array comprises a plurality of integrated circuit modules, each comprising a plurality of integrated circuit chips. The sensor modules may be coupled to the electronics modules via flip chip technology.

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract: A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive method does not require the use of a solder mask, does not require the melting of the bulk of any of the solder balls and does not require the use of a fluxing agent.

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.