Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract: A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive method does not require the use of a solder mask, does not require the melting of the bulk of any of the solder balls and does not require the use of a fluxing agent.

Abstract: Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement.

Abstract: A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive method does not require the use of a solder mask, does not require the melting of the bulk of any of the solder balls and does not require the use of a fluxing agent.

Abstract: Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement.

Abstract: A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive method does not require the use of a solder mask, does not require the melting of the bulk of any of the solder balls and does not require the use of a fluxing agent.

Abstract: A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive method does not require the use of a solder mask, does not require the melting of the bulk of any of the solder balls and does not require the use of a fluxing agent.

Abstract: Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which may be stabilized by transient liquid phase (TLP) processes and preferably with or during metallization of conductive pads, possibly including connector patterns on both sides of at least some of the chips in the stack. At least some of the chips in the stack then have electrical and mechanical connections made therebetween, preferably with electroplated solder preforms consistent with TLP processes. The connections may be contained by a layer of resilient material surrounding the connections and which may be formed in-situ. High density circuit packages thus obtained may be mounted on a carrier by surface mount techniques or separable connectors such as a plug and socket arrangement.

Abstract: A multilayer circuit board system or laminated circuit board system for use in a motor controller includes at least two motherboards, at least one power substrate circuit board, and a capacitor circuit board. The circuit boards are mounted in an aperture or trench within each mother board. The power substrate module circuit board includes a mounting area provided in a recess, window or portion of the circuit board where the circuit board is only a single layer thick. The single circuit board layer at the mounting area provides a heat conductive yet highly electrically insulated mounting area for receiving a heat sink. The heat sink can be mounted on a side opposite the electrical device. The capacitor circuit board, power substrate circuit board, and mother circuit boards are interconnected without the use of external connectors or wires. The use of two mother boards increases the rigidity of the circuit board system.

Abstract: A mounting for a solderable component module (SCM.TM.) interconnect module includes an elongated trench or blind via for receiving an edge of the module. The module may be a circuit board or other electrical device and preferably includes edge finger connectors. The elongated trench preferably includes hemicylinders located about the periphery. The hemicylinders provide plated through conductors for connecting to the finger connectors of the module. The trench is made according to an advantageous method in which the aperture is etched in order to remove barbs or extra copper material caused by milling the aperture. Preferably, the module fits into the trench with an interference or size-on-size fit. The trench may include strain relief areas. Additionally, the mounting can include apertures for receiving legs on the mounted board.

Abstract: The present invention provides a solder alloy having from about 80-81% tin, from about 2-4% silver, from about 5-6% indium, and from about 10-12% bismuth by weight, and microelectric circuits soldered by this alloy.

Abstract: A metallurgical bond which may be substituted for a soldering process forms an alloy of a metal with a metal coating applied to at least one of the surfaces to be so bonded by a transient liquid phase (TLP) reaction at a low temperature. Mechanically robust bonding of noble metals for electrical connections which are resistively stable through repeated thermal cycling can be performed at particularly low temperatures using coating materials of indium, tin or lead. Isotropically or anisotropically conductive connections can be formed by applying a polymer adhesive containing conductive particles to at least one of the surfaces to be bonded and a compressional force developed between surface by curing of the polymer adhesive at temperatures lower than the melting point of a eutectic alloy of the chosen metal system before the TLP process is allowed to proceed.

Abstract: A multilayer circuit board system or laminated circuit board system for use in a motor controller includes a motherboard, at least one power substrate circuit board, and a capacitor circuit board. The power substrate module includes a mounting area provided in a recess, window or portion of the circuit board where the circuit board is only a single layer thick. The single circuit board layer at the mounting area provides a heat conductive yet highly electrically insulated mounting area for receiving a heat sink. The heat sink can be mounted on a side opposite the electrical device. The capacitor circuit board, power substrate circuit board, and mother circuit board are interconnected without the use of external connectors or wires. A flexible circuit board layer or SCM.TM. interconnect interface allows the circuit boards to be connected solely by printed circuit (PC) wires.

Abstract: A solder resist pattern for a single in-line package (SIP) finger connector, or other interface member includes small solder resist features spaced closely together. The features can be circular, square, diamond-shaped, star-shaped, or other geometry and preferably are placed on finger connectors in a photo-imaging process. The pattern includes meniscus channels which are narrow enough to prevent solder from adhering to the finger connectors. The surface area of the features is small enough so that the pattern can be easily removed by a low impact or non-contact operation. Preferably, the pattern is removed by a hot air solder knife after the board is subjected to a solder wave.

Abstract: A mounting for a solderable component module (SCM.TM.) interconnect includes an elongated trench or blind via for receiving an edge of the module. The interconnect may be adjusted to reduce the parasitic inductance associated with the connection of the SCM interconnect and the motherboard. Preferably, the design of the finger connectors associated with the SCM interconnect or other board module can be adjusted to reduce parasitic inductance. Alternatively, the capacitance associated with the SCM interconnect or motherboard may be adjusted. The SCM interconnect preferably includes finger connectors which have a rectangular shape. The finger connectors preferably have a shape wherein the length is greater than the width and have an enhanced thickness which reduces parasitic inductance. The finger connectors are spaced close together.

Abstract: A mounting for a single in-line package (SIP) module includes an elongated slot aperture for receiving an edge of the module. The module may be a circuit board or other electrical device and preferably includes edge finger connectors. The elongated slot aperture preferably includes hemicylinders located about the periphery. The hemicylinders provide plated through conductors for connecting to the finger connectors of the module. The aperture is made according to an advantageous method in which the aperture is etched in order to remove barbs or extra copper material caused by milling the aperture. Preferably, the module fits into the aperture with an interference or size-on-size fit. The aperture may include strain relief areas.

Abstract: A mounting for a single in-line package (SIP) module includes an elongated slot aperture for receiving an edge of the module. The module may be a circuit board or other electrical device and preferably includes edge finger connectors. The elongated slot aperture preferably includes hemicylinders located about the periphery. The hemicylinders provide plated through conductors for connecting to the finger connectors of the module. The aperture is made according to an advantageous method in which the aperture is etched in order to remove barbs or extra copper material caused by milling the aperture. Preferably, the module fits into the aperture with an interference or size-on-size fit. The aperture may include strain relief areas.