Abstract: A method and system to build a control flow graph by execution of micro-sequences using hardware. Some illustrative embodiments are a processor comprising fetch logic that retrieves an instruction from a memory, the instruction being part of a program, and decode logic coupled to the fetch logic which decodes the instruction, wherein the instruction decoded by the decode logic triggers execution of a micro-sequence to enter the instruction in a control flow graph.

Abstract: Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.

Abstract: A processor adapted to couple to external memory. The processor comprises a controller and data storage. The data storage is usable to store local variables and temporary data and is configurable to operate in either a cache policy mode in which a miss results in an access of the external memory or in a scratch pad policy mode in which a miss does not result in an access of the external memory. The data storage comprises first and second portions, and wherein only one of said portions is active at a time for storing said local variables. When the active portion does not have sufficient capacity for additional local variables, the other portion becomes the active portion for storing local variables. When one portion is the active portion, the other portion is used to store the temporary data and such other portion is sufficiently large to contain the temporary data.

Abstract: A method and system of informing a micro-sequence of operand width. At least some of the illustrative embodiments may be a method comprising fetching a first opcode, asserting a flag if the first opcode modifies an operand width of a subsequent opcode, fetching a second opcode, triggering a micro-sequence based on the opcode, reading the flag by instructions of the micro-sequence, and fetching an operand of the second opcode by the micro-sequence (the bit width of the operand based on a state of the flag).

Abstract: A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.

Abstract: In some embodiments, a processor comprises fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine.

Abstract: A method and related system of using a “WIDE” opcode as other than a prefix. At least some of the illustrative embodiments may be a method comprising fetching an opcode (the opcode used in at least some circumstances as a prefix to other opcodes), and determining whether the opcode is used as a prefix. If the opcode is not used as the prefix, then the method further comprises executing the opcode; or replacing the opcode by a group of other instructions.

Abstract: A system comprising an interrupt logic comprising a data structure and adapted to process a plurality of interrupt requests, and a plurality of processor cores coupled to the interrupt logic. The data structure comprises a plurality of entries, each entry corresponding to a different interrupt request and having multiple fields. The interrupt logic receives an interrupt request and selectively transfers the interrupt request to one of the plurality of processor cores as indicated by a first field of an entry corresponding to said interrupt request. The one of the plurality of processor cores services the interrupt request.

Abstract: A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit and stores the operand to the second storage unit for use by the group of instructions.

Abstract: A processor executes a load (or store) instruction that permits optional error checking to be performed. Based on a control bit in the load instruction, the processor executes the load instruction by causing contents of a source register to be compared to a predetermined value. If the contents of the source register equals the predetermined value, the processor executes an exception handler.

Abstract: A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for determining whether an attempted access (either a load or write) to an array improperly targets a location outside the boundary of the array. In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.

Abstract: An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum amount of information needed to resume execution of the first thread at the switch point and not information not needed to resume execution of the first thread at the switch point.

Abstract: A system comprising a processor containing a first stack internal to a core of the processor, at least some data values in the first stack corresponding to values in a second stack external to the core. The system also comprises a memory coupled to the processor. In an iterative process, the processor pops a data value off of the first stack and begins to store the data value to the memory while the processor begins to use an existing data value from the first stack to produce a new data value to be stored on the first stack.

Abstract: A processor executes an instruction that causes a source data field from a first source register to be copied to a destination register at a programmable position within the destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.

Abstract: A method and system to emulate an M-bit instruction set. At least some of the illustrative embodiments are a method comprising fetching at least a portion of an instruction (the instruction from a first instruction set that is not directly executable by a processor), indexing into a table to an index location (the index location based on the at least a portion of the instruction), executing a first series of instructions directly executable by the processor (the first series of instructions pointed to by the table at the index location), and thereby emulating execution of the instruction from the first instruction set.

Abstract: A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch logic and adapted to process the set of instructions, and a clock coupled to the decode logic. When processed, an instruction from the set causes the clock to increment a counter external to the processor while the subset is processed. A status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions.

Abstract: An electronic device comprising a first processor and a second processor, the second processor coupled to the first processor and adapted to receive an address from the first processor, to pause execution of a first thread at a switch point, and to use the address to retrieve and execute a group of instructions in a second thread. Prior to executing the group of instructions in the second thread, the second processor pushes onto a hardware-controlled stack data pertaining to the switch point, the data comprising information needed to resume execution of the first thread at the switch point.

Abstract: Systems, methods, and computer-readable media for interrupt handling in Java are provided. In some illustrative embodiments, a system is provided that includes a Java execution flow class that represents an execution flow context, an execution flow scheduler object including a Java native execution flow activation method, a Java virtual machine, and an interrupt handler class that extends the execution flow class. The execution flow class includes an execution flow execution method and a constructor that creates an execution flow context. The interrupt handler class includes a handler method and an execution flow execution method that overrides the execution flow execution method of the execution flow class.

Abstract: An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.

Abstract: The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.