Interrupt management in dual core processors

Abstract

A system comprising an interrupt logic comprising a data structure and adapted to process a plurality of interrupt requests, and a plurality of processor cores coupled to the interrupt logic. The data structure comprises a plurality of entries, each entry corresponding to a different interrupt request and having multiple fields. The interrupt logic receives an interrupt request and selectively transfers the interrupt request to one of the plurality of processor cores as indicated by a first field of an entry corresponding to said interrupt request. The one of the plurality of processor cores services the interrupt request.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to European Patent Application No. 04291918.3, filed on Jul. 27, 2004 and incorporated herein by reference. This application is related to co-pending and commonly assigned applications Ser. No. ______ (Attorney Docket No. TI-38581 (1962-22200)), entitled, “Emulating A Direct Memory Access Controller,” and Ser. No. ______ (Attorney Docket No. TI-38583 (1962-22400), entitled, “Delegating Tasks Between Multiple Processor Cores,” which are incorporated by reference herein.

BACKGROUND

Computer systems may comprise multiple processors. The processors may share tasks and also may execute tasks independent of one another. For example, one of the processors may be used to run an operating system while the other processor is used to execute software instructions of a particular type (e.g., Java™ Bytecode instructions). Often, the operating system or a hardware component in the computer system may generate a request for a particular task to be completed. This task may be of a higher priority level than the tasks being executed in the processors, and thus one of the processors may need to be “interrupted” so that the processor may execute the higher-priority task. A request for such a high-priority task to be executed is an “interrupt request.” Interrupt requests are serviced by a single processor that is dedicated to servicing interrupt requests. However, consistently servicing interrupt requests using the processor dedicated to servicing interrupt requests is not the most efficient manner in which to service interrupt requests.

BRIEF SUMMARY

Disclosed herein is a technique for selectively servicing interrupts on one of a plurality of processors. An illustrative embodiment comprises a system comprising an interrupt logic comprising a data structure and adapted to process a plurality of interrupt requests, and a plurality of processor cores coupled to the interrupt logic. The data structure comprises a plurality of entries, each entry corresponding to a different interrupt request and having multiple fields. The interrupt logic receives an interrupt request and selectively transfers the interrupt request to one of the plurality of processor cores as indicated by a first field of an entry corresponding to said interrupt request. The one of the plurality of processor cores services the interrupt request.

Another illustrative embodiment comprises an electronic device comprising a data structure including a plurality of entries, at least one entry corresponding to an interrupt request and comprising a first field and a second field. The electronic device receives the interrupt request and selectively transfers the interrupt request to a single processor selected from a plurality of processors as indicated by contents of the first field. The single processor retrieves a group of instructions from a memory location specified by the second field. When executed, the group of instructions causes the single processor to pause execution of a thread, to service the interrupt request, and to resume execution of the thread.

Yet another illustrative embodiment includes a method comprising transferring multiple interrupt requests to an interrupt logic comprising a data structure, at least some of the multiple interrupt requests inserted into the data structure, selecting a particular interrupt request from among the multiple interrupt requests, the particular interrupt request corresponding to multiple fields, interrupting a single processor selected from a plurality of processors as indicated by a first field of the particular interrupt request, servicing the particular interrupt request on the single processor, and transferring an acknowledgement signal to the interrupt logic upon servicing the particular interrupt request.

Notation and Nomenclature

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein:

FIG. 1 shows a diagram of a system in accordance with preferred embodiments of the invention and including a Java Stack Machine (“JSM”) and a Main Processor Unit (“MPU”), in accordance with embodiments of the invention;

FIG. 2 shows a block diagram of the JSM of FIG. 1 in accordance with embodiments of the invention;

FIG. 3 shows various registers used in the JSM of FIGS. 1 and 2, in accordance with embodiments of the invention;

FIG. 4 shows the preferred operation of the JSM to include “micro-sequences,” in accordance with embodiments of the invention;

FIG. 5 shows a modified diagram of the system of FIG. 1, in accordance with a preferred embodiment of the invention;

FIG. 6 shows a data structure used in the system of FIG. 5 to selectively interrupt one of a plurality of processor cores, in accordance with a preferred embodiment of the invention;

FIG. 7 shows a flow diagram in accordance with embodiments of the invention; and

FIG. 8 shows the system described herein, in accordance with preferred embodiments of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

Described herein is an electronic device used to selectively transfer interrupt requests to one of a plurality of processors. Also described herein is a technique by which the selected processor is able to store information pertaining to a thread being executed when the interrupt request is received, whereupon the thread is preempted and the interrupt request is serviced. After the processor services the interrupt request, the processor uses the minimal amount of information to resume executing the thread as before the interrupt request was received.

The information pertaining to the thread preferably is a minimal amount of information necessary to resume executing the thread after servicing the interrupt request. A “minimal” amount of information generally comprises information in one or more registers, but not all registers, of a processor core. For example, in some embodiments, a “minimal” amount of information comprises a program counter (PC) register, a micro-program counter (μPC) register and a status register. In other embodiments, a “minimal” amount of information comprises the PC register, the μPC register and the status register, as well as one or more additional registers, but less than all registers. In still other embodiments, a “minimal” amount of information comprises less than all registers. In yet other embodiments, a “minimal” amount of information varies depending on the processor used and/or the software application being processed. In such cases, the “minimal” amount of information may simply be one register or may be all of the registers in the processor core.

The processor described herein is particularly suited for executing Java™ Bytecodes or comparable code. As is well known, Java is particularly suited for embedded applications. Java is a relatively “dense” language meaning that on average each instruction may perform a large number of functions compared to various other programming languages. The dense nature of Java is of particular benefit for portable, battery-operated devices that preferably include as little memory as possible to save space and power. The reason, however, for executing Java code is not material to this disclosure or the claims which follow. Further, the processor advantageously includes one or more features that permit the execution of the Java code to be accelerated.

Referring now to FIG. 1, a system 100 is shown in accordance with a preferred embodiment of the invention. As shown, the system includes at least two processors 102 and 104. Processor 102 is referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) and processor 104 may be referred to as a Main Processor Unit (“MPU”). System 100 may also include memory 106 coupled to both the JSM 102 and MPU 104 and thus accessible by both processors. At least a portion of the memory 106 may be shared by both processors meaning that both processors may access the same shared memory locations. Further, if desired, a portion of the memory 106 may be designated as private to one processor or the other. System 100 also includes a Java Virtual Machine (“JVM”) 108, compiler 110, and a display 114. The MPU 104 preferably includes an interface to one or more input/output (“I/O”) devices such as a keypad to permit a user to control various aspects of the system 100. In addition, data streams may be received from the I/O space into the JSM 102 to be processed by the JSM 102. Other components (not specifically shown) may be included as desired for various applications.

As is generally well known, Java code comprises a plurality of “Bytecodes” 112. Bytecodes 112 may be provided to the JVM 108, compiled by compiler 110 and provided to the JSM 102 and/or MPU 104 for execution therein. In accordance with a preferred embodiment of the invention, the JSM 102 may execute at least some, and generally most, of the Java Bytecodes. When appropriate, however, the JSM 102 may request the MPU 104 to execute one or more Java Bytecodes not executed or executable by the JSM 102. In addition to executing Java Bytecodes, the MPU 104 also may execute non-Java instructions. The MPU 104 also hosts an operating system (“O/S”) (not specifically shown) which performs various functions including system memory management, the system task management that schedules the JVM 108 and most or all other native tasks running on the system, management of the display 114, receiving input from input devices, etc. Without limitation, Java code may be used to perform any one of a variety of applications including multimedia, games or web based applications in the system 100, while non-Java code, which may comprise the O/S and other native applications, may still run on the system on the MPU 104.

The JVM 108 generally comprises a combination of software and hardware. The software may include the compiler 110 and the hardware may include the JSM 102. The JVM may include a class loader, Bytecode verifier, garbage collector, and a Bytecode interpreter loop to interpret the Bytecodes that are not executed on the JSM processor 102.

In accordance with preferred embodiments of the invention, the JSM 102 may execute at least two types of instruction sets. One type of instruction set may comprise standard Java Bytecodes. As is well-known, Java is a stack-based programming language in which instructions generally target a stack. For example, an integer add (“IADD”) Java instruction pops two integers off the top of the stack, adds them together, and pushes the sum back on the stack. A “simple” Bytecode instruction is generally one in which the JSM 102 may perform an immediate operation either in a single cycle (e.g., an “iadd” instruction) or in several cycles (e.g., “dup2_x2”). A “complex” Bytecode instruction is one in which several memory accesses may be required to be made within the JVM data structure for various verifications (e.g., NULL pointer, array boundaries). As will be described in further detail below, one or more of the complex Bytecodes may be replaced by a “micro-sequence” comprising various other instructions.

Another type of instruction set executed by the JSM 102 may include instructions other than standard Java instructions. In accordance with at least some embodiments of the invention, the other instruction set may include register-based and memory-based operations to be performed. This other type of instruction set generally complements the Java instruction set and, accordingly, may be referred to as a complementary instruction set architecture (“C-ISA”). By complementary, it is meant that a complex Java Bytecode may be replaced by a “micro-sequence” comprising C-ISA instructions. The execution of Java may be made more efficient and run faster by replacing some sequences of Bytecodes by preferably shorter and more efficient sequences of C-ISA instructions. The two sets of instructions may be used in a complementary fashion to obtain satisfactory code density and efficiency. As such, the JSM 102 generally comprises a stack-based architecture for efficient and accelerated execution of Java Bytecodes combined with a register-based architecture for executing register and memory based C-ISA instructions. Both architectures preferably are tightly combined and integrated through the C-ISA. Because various of the data structures described herein are generally JVM-dependent and thus may change from one JVM implementation to another, the software flexibility of the micro-sequence provides a mechanism for various JVM optimizations now known or later developed.

FIG. 2 shows an exemplary block diagram of the JSM 102. As shown, the JSM includes a core 120 coupled to data storage 122 and instruction storage 130. The core may include one or more components as shown. Such components preferably include a plurality of registers 140, three address generation units (“AGUs”) 142, 147, micro-translation lookaside buffers (micro-TLBs) 144, 156, a multi-entry micro-stack 146, an arithmetic logic unit (“ALU”) 148, a multiplier 150, decode logic 152, and instruction fetch logic 154. In general, operands may be retrieved from data storage 122 or from the micro-stack 146 and processed by the ALU 148, while instructions may be fetched from instruction storage 130 by fetch logic 154 and decoded by decode logic 152. The address generation unit 142 may be used to calculate addresses based, at least in part, on data contained in the registers 140. The AGUs 142 may calculate addresses for C-ISA instructions. The AGUs 142 may support parallel data accesses for C-ISA instructions that perform array or other types of processing. The AGU 147 couples to the micro-stack 146 and may manage overflow and underflow conditions in the micro-stack preferably in parallel. The micro-TLBs 144, 156 generally perform the function of a cache for the address translation and memory protection information bits that are preferably under the control of the operating system running on the MPU 104. The decode logic 152 comprises auxiliary registers 151.

Referring now to FIG. 3, the registers 140 may include 16 registers designated as R0-R15. In some embodiments, registers R0-R5 and R8-R14 may be used as general purposes (“GP”) registers usable for any purpose by the programmer. Other registers, and some of the GP registers, may be used for specific functions. For example, in addition to use as a GP register, register R5 may be used to store the base address of a portion of memory in which Java local variables may be stored when used by the current Java method. The top of the micro-stack 146 can be referenced by the values in registers R6 and R7. The top of the micro-stack 146 has a matching address in external memory pointed to by register R6. The values contained in the micro-stack 146 are the latest updated values, while their corresponding values in external memory may or may not be up to date. Register R7 provides the data value stored at the top of the micro-stack 146. Register R15 may be used for status and control of the JSM 102. At least one bit (called the “Micro-Sequence-Active” bit) in status register R15 is used to indicate whether the JSM 102 is executing a simple instruction or a complex instruction through a micro-sequence. This bit controls, in particular, which program counter is used (PC or μPC) to fetch the next instruction, as will be explained below.

Referring again to FIG. 2, as noted above, the JSM 102 is adapted to process and execute instructions from at least two instruction sets, at least one having instructions from a stack-based instruction set (e.g., Java). The stack-based instruction set may include Java Bytecodes. Unless empty, Java Bytecodes may pop data from and push data onto the micro-stack 146. The micro-stack 146 preferably comprises the top n entries of a larger stack that is implemented in data storage 122. Although the value of n may vary in different embodiments, in accordance with at least some embodiments, the size n of the micro-stack may be the top eight entries in the larger, memory-based stack. The micro-stack 146 preferably comprises a plurality of gates in the core 120 of the JSM 102. By implementing the micro-stack 146 in gates (e.g., registers) in the core 120 of the processor 102, access to the data contained in the micro-stack 146 is generally very fast, although any particular access speed is not a limitation on this disclosure.

The ALU 148 adds, subtracts, and shifts data. The multiplier 150 may be used to multiply two values together in one or more cycles. The instruction fetch logic 154 generally fetches instructions from instruction storage 130. The instructions may be decoded by decode logic 152. Because the JSM 102 is adapted to process instructions from at least two instruction sets, the decode logic 152 generally comprises at least two modes of operation, one mode for each instruction set. As such, the decode logic unit 152 may include a Java mode in which Java instructions may be decoded and a C-ISA mode in which C-ISA instructions may be decoded.

The data storage 122 generally comprises data cache (“D-cache”) 124 and data random access memory (“DRAM”) 126. Reference may be made to U.S. Pat. No. 6,826,652, filed Jun. 9, 2000 and U.S. Pat. No. 6,792,508, filed Jun. 9, 2000, both incorporated herein by reference. Reference also may be made to U.S. Ser. No. 09/932,794 (Publication No. 20020069332), filed Aug. 17, 2001 and incorporated herein by reference. The stack (excluding the micro-stack 146), arrays and non-critical data may be stored in the D-cache 124, while Java local variables, critical data and non-Java variables (e.g., C, C++) may be stored in D-RAM 126. The instruction storage 130 may comprise instruction RAM (“I-RAM”) 132 and instruction cache (“I-cache”) 134. The I-RAM 132 may be used for “complex” micro-sequenced Bytecodes or micro-sequences, as described below. The I-cache 134 may be used to store other types of Java Bytecode and mixed Java/C-ISA instructions.

As noted above, the C-ISA instructions generally complement the standard Java Bytecodes. For example, the compiler 110 may scan a series of Java Bytecodes 112 and replace a complex Bytecode with a micro-sequence as explained previously. The micro-sequence may be created to optimize the function(s) performed by the replaced complex Bytecodes.

FIG. 4 illustrates the operation of the JSM 102 to replace Java Bytecodes with micro-sequences. FIG. 4 shows some, but not necessarily all, components of the JSM. In particular, the instruction storage 130, the decode logic 152, and a micro-sequence vector table 162 are shown. The decode logic 152 receives instructions from the instruction storage 130 and accesses the micro-sequence vector table 162. In general and as described above, the decode logic 152 receives instructions (e.g., instructions 170) from instruction storage 130 via instruction fetch logic 154 (FIG. 2) and decodes the instructions to determine the type of instruction for subsequent processing and execution. In accordance with the preferred embodiments, the JSM 102 either executes the Bytecode from instructions 170 or replaces a Bytecode from instructions 170 with a micro-sequence as described below.

The micro-sequence vector table 162 may be implemented in the decode logic 152 or as separate logic in the JSM 102. The micro-sequence vector table 162 preferably includes a plurality of entries 164. The entries 164 may include one entry for each Bytecode that the JSM may receive. For example, if there are a total of 256 Bytecodes, the micro-sequence vector table 162 preferably comprises at least 256 entries. Each entry 164 preferably includes at least two fields—a field 166 and an associated field 168. Field 168 may comprise a single bit that indicates whether the instruction 170 is to be directly executed or whether the associated field 166 contains a reference to a micro-sequence. For example, a bit 168 having a value of “0” (“not set”) may indicate the field 166 is invalid and thus, the corresponding Bytecode from instructions 170 is directly executable by the JSM. Bit 168 having a value of “1” (“set”) may indicate that the associated field 166 contains a reference to a micro-sequence.

If the bit 168 indicates the associated field 166 includes a reference to a micro-sequence, the reference may comprise the full starting address in instruction storage 130 of the micro-sequence or a part of the starting address that can be concatenated with a base address that may be programmable in the JSM. In the former case, field 166 may provide as many address bits as are required to access the full memory space. In the latter case, a register within the JSM registers 140 is programmed to hold the base address and the vector table 162 may supply only the offset to access the start of the micro-sequence. Most or all JSM internal registers 140 and any other registers preferably are accessible by the main processor unit 104 and, therefore, may be modified by the JVM as necessary. Although not required, this latter addressing technique may be preferred to reduce the number of bits needed within field 166. At least a portion 180 of the instruction 130 may be allocated for storage of micro-sequences and thus the starting address may point to a location in micro-sequence storage 130 at which a particular micro-sequence can be found. The portion 180 may be implemented in I-RAM 132 shown above in FIG. 2.

Although the micro-sequence vector table 162 may be loaded and modified in accordance with a variety of techniques, the following discussion includes a preferred technique. The vector table 162 preferably comprises a JSM resource that is addressable via a register 140. A single entry 164 or a block of entries within the vector table 162 may be loaded by information from the data cache 124 (FIG. 2). When loading multiple entries (e.g., all of the entries 164) in the table 162, a repeat loop of instructions may be executed. Prior to executing the repeat loop, a register (e.g., R0) preferably is loaded with the starting address of the block of memory containing the data to load into the table. Another register (e.g., R1) preferably is loaded with the size of the block to load into the table. Register R14 is loaded with the value that corresponds to the first entry in the vector table that is to be updated/loaded.

The repeated instruction loop preferably comprises two instructions that are repeated n times. The value n preferably is the value stored in register R1. The first instruction in the loop preferably performs a load from the start address of the block (R0) to the first entry in the vector table 162. The second instruction in the loop preferably adds an “immediate” value to the block start address. The immediate value may be “2” if each entry in the vector table is 16 bits wide. The loop repeats itself to load the desired portions of the total depending on the starting address.

In operation, the decode logic 152 uses a Bytecode from instructions 170 as an index into micro-sequence vector table 162. Once the decode logic 152 locates the indexed entry 164, the decode logic 152 examines the associated bit 168 to determine whether the Bytecode is to be replaced by a micro-sequence. If the bit 168 indicates that the Bytecode can be directly processed and executed by the JSM, then the instruction is so executed. If, however, the bit 168 indicates that the Bytecode is to be replaced by a micro-sequence, then the decode logic 152 preferably changes this instruction into a “no operation” (NOP) and sets the micro-sequence-active bit (described above) in the status register R15. In another embodiment, the JSM's pipe may be stalled to fetch and replace this micro-sequenced instruction by the first instruction of the micro-sequence. Changing the micro-sequenced Bytecode into a NOP while fetching the first instruction of the micro-sequence permits the JSM to process multi-cycle instructions that are further advanced in the pipe without additional latency. The micro-sequence-active bit may be set at any suitable time such as when the micro-sequence enters the JSM execution stage (not specifically shown).

As described above, the JSM 102 implements two program counters—the PC and the μPC. The PC and the μPC are stored in auxiliary registers 151, which in turn is stored in the decode logic 152. In accordance with a preferred embodiment, one of these two program counters is the active program counter used to fetch and decode instructions. The PC 186 may be the currently active program counter when the decode logic 152 encounters a Bytecode to be replaced by a micro-sequence. Setting the status register's micro-sequence-active bit causes the micro-program counter 188 to become the active program counter instead of the program counter 186. Also, the contents of the field 166 associated with the micro-sequenced Bytecode preferably are loaded into the μPC 188. At this point, the JSM 102 is ready to begin fetching and decoding the instructions comprising the micro-sequence. At or about the time the decode logic begins using the μPC 188, the PC 186 preferably is incremented by a suitable value to point the PC 186 to the next instruction following the Bytecode that is replaced by the micro-sequence. In at least some embodiments, the micro-sequence-active bit within the status register R15 may only be changed when the first instruction of the micro-sequence enters the execute phase of JSM 102 pipe. The switch from PC 186 to the μPC 188 preferably is effective immediately after the micro-sequenced instruction is decoded, thereby reducing the latency.

The micro-sequence may end with a predetermined value or Bytecode from the C-ISA called “RtuS” (return from micro-sequence) that indicates the end of the sequence. This C-ISA instruction causes a switch from the μPC 188 to the PC 186 upon completion of the micro-sequence. Preferably, the PC 186 previously was incremented, as discussed above, so that the value of the PC 186 points to the next instruction to be decoded. The instruction may have a delayed effect or an immediate effect depending on the embodiment that is implemented. In embodiments with an immediate effect, the switch from the μPC 188 to the PC 186 is performed immediately after the instruction is decoded and the instruction after the RtuS instruction is the instruction pointed to by the address present in the PC 186.

As discussed above, one or more Bytecodes may be replaced with a micro-sequence or a group of other instructions. Such replacement instructions may comprise any suitable instructions for the particular application and situation at hand. At least some such suitable instructions are disclosed in U.S. Ser. No. 10/631,308 (Publication No. 20040024989), filed Jul. 31, 2003 and incorporated herein by reference.

Interrupt requests may be selectively delivered to either the JSM 102 or the MPU 104 as follows. FIG. 5 shows a system 800 similar to the system 100 of FIG. 1, with the exception of an interrupt controller 802 (e.g., an application-specific integrated circuit or other suitable logic) coupled to the JSM 102 and the MPU (i.e., ARM) 104. The interrupt controller 802 receives software interrupt requests from an operating system (“OS”) in the MPU 104 and hardware interrupt requests from various hardware components in the system 800, some of which may not be shown in FIG. 5. In turn, the interrupt controller 802 selectively interrupts the JSM 102 or the MPU 104 based on which of the two processor cores would most efficiently service the received hardware or software interrupt request. More specifically, the interrupt controller 802 determines which processor core is to service the interrupt request by using an interrupt vector table (IVT) 804 stored in the interrupt controller 802 or in any other suitable location. In some embodiments, the MPU 104 may service a portion of an interrupt request and then transfer a signal to the JSM 102 that causes the JSM 102 to finish servicing the interrupt request.

FIG. 6 shows the IVT 804 in detail. The IVT 804 (e.g., a data structure) comprises a plurality of entries 812, which entries 812 preferably are arranged in order of priority. In turn, each entry 812 comprises at least three fields 806, 808, 810. Field 806 comprises a bit that indicates whether the corresponding interrupt request should be serviced by the JSM 102 or the MPU 104. In some embodiments, an asserted field 806 (i.e., set to “1”) indicates that the JSM 102 is to handle the corresponding interrupt request, and an unasserted field 806 (i.e., set to “0”) indicates that the MPU 104 is to handle the corresponding interrupt request. Other bit configurations also are possible and the scope of disclosure is not limited to any particular bit configuration. For instance, field 806 may comprise more than one bit, depending on the number of processors coupled to interrupt controller 802.

The field 808 comprises a bit that is assigned based on whether the corresponding entry 812 interrupt has been serviced or not. In some embodiments, if the interrupt corresponding to entry 812 has been serviced, the field 808 comprises a “0” bit if the interrupt is pending, and a “1” bit if the interrupt has been serviced. In other embodiments, the field 808 comprises a “0” bit if the interrupt has been serviced, and a “1” bit if the interrupt is pending. The field 808 preferably is set or reset by an acknowledge signal 814 received by the interrupt controller 802 from the JSM 102, which acknowledge signal is sent by the JSM 102 when a corresponding interrupt has been serviced. Although not specifically shown, in some embodiments, the interrupt controller 802 may receive acknowledge signals (similar to acknowledge signal 814) from both the JSM 102 and the MPU 104, or possibly just from the MPU 104 and not from the JSM 102.

The contents of field 810 depend on the status of field 806. If the field 806 indicates that a corresponding interrupt request is to be serviced by the MPU 104, then the field 810 comprises an interrupt vector to pass to MPU 104. Using the interrupt vector, the MPU 104 locates the instructions used to service the interrupt request and proceeds to decode and execute these instructions. These instructions, when executed, enable the MPU 104 to service the interrupt request. However, if the field 806 indicates that the corresponding interrupt request is to be serviced by the JSM 102, then the field 810 comprises the address of a micro-sequence (i.e., interrupt handler) that may be used to service the interrupt request.

More specifically, the JSM 102 may be interrupted by the interrupt controller 802 while the JSM 102 is executing instructions (e.g., software instructions) in a thread. When the interrupt controller 802 interrupts the JSM 102, the interrupt controller 802 retrieves the address of the interrupt handler stored in field 810 and transfers this address to the JSM 102. The JSM 102 first preempts the thread. The JSM 102 then stores the appropriate registers 140 on a suitable stack (e.g., T1 stack 123). As previously discussed, the JSM 102 preferably stores the PC 186, the μPC 188, and the status register R15. However, the scope of disclosure is not limited to storing this specific combination of registers and the JSM 102 may store any of the registers 140 as necessary. In this way, the “context” of the thread is stored. The JSM 102 then uses the interrupt handler address to retrieve and execute the interrupt handler micro-sequence stored in the instruction storage 130. As previously noted, the interrupt handler may comprise a plurality of instructions which, when executed, enable the JSM 102 to service the interrupt. Because it is a micro-sequence, the interrupt handler uses the μPC 188 as a program counter during execution. In addition to servicing the interrupt request, the interrupt handler also may cause the JSM 102 to push additional register values onto the T1 stack 123. When the JSM 102 is finished servicing the interrupt request, the interrupt handler causes the JSM 102 to resume execution of the thread by first popping register values (e.g., PC 186, μPC 188, status register R15) off of the micro-stack 146 and storing the register values to the appropriate registers in the JSM 102.

FIG. 7 shows a flowchart summarizing the process used to service an interrupt request on the JSM 102. The process 600 may begin by processing thread T1 (block 602). The process 600 comprises monitoring for an interruption of thread T1 (block 604). The thread T1 may be interrupted for any of the reasons described above. If the thread T1 has not been interrupted, then the process 600 comprises continuing to process thread T1 (block 602). However, if the thread T1 has been interrupted, then the process 600 comprises halting (i.e., pre-empting) processing of thread T1 (block 606) and pushing at least some registers 140 onto the T1 stack 123 (block 608), thus saving the context of the thread T1. Although the scope of disclosure is not limited to pushing any particular combination of register values onto the T1 stack 123, in at least some embodiments, the PC 186, the μPC 188 and the status register R15, and preferably an additional register 140 are pushed onto the stack, since it is expedient to transfer four register values at a time. Once the register values are pushed onto the T1 stack 123, the JSM 102 loads the interrupt handler micro-sequence and executes the micro-sequence (block 610). Executing the micro-sequence enables the JSM 102 to service the interrupt request. After the interrupt request is serviced, the interrupt handler micro-sequence pops the register values (i.e., stored on the T1 stack 123) off of the T1 stack 123 and stores the register values to the appropriate registers 140 (block 612), thus restoring the aforementioned context of thread T1. The JSM 102 then may resume executing the thread it was executing when it received the interrupt request (block 614).

In the embodiments described above, a minimum context of register values (i.e., PC, μPC, status registers) is pushed onto a stack prior to servicing an interrupt request. While storing the minimum-context is faster than storing a full-context (i.e., all registers in the JSM core), in some embodiments, it may be desirable to perform a full-context store instead of a minimum-context store, for reasons previously described. Thus, in such embodiments, full contexts also may be stored and/or loaded, in which case most or all of the registers 140 as well as most or all of the auxiliary registers 151 are stored and/or loaded prior to the servicing of each interrupt request. For instance, in cases where one or more register values other than the PC 186, μPC 188, and status register are used by the interrupt handler micro-sequence, it may be desirable to store all register values via a full-context store. A full-context store and/or load is performed in a similar manner to a minimum-context store and/or load, with the exception being a difference in the number of registers stored and/or loaded.

System 100 may be implemented as a battery-operated mobile (i.e., wireless) communication device (e.g., a mobile phone) 415 such as that shown in FIG. 8. As shown, the mobile communication device includes an integrated keypad 412 and display 414. The JSM 102, the MPU 104, the interrupt controller 802 and other components may be included in electronics package 410 connected to the keypad 412, display 414, and radio frequency (“RF”) circuitry 416. The RF circuitry 416 may be connected to an antenna 418.

While the preferred embodiments of the present invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The embodiments described herein are exemplary only, and are not intended to be limiting. Many variations and modifications of the invention disclosed herein are possible and are within the scope of the invention. Accordingly, the scope of protection is not limited by the description set out above. Each and every claim is incorporated into the specification as an embodiment of the present invention.

Claims

1. A system, comprising:

an interrupt logic comprising a data structure and adapted to process a plurality of interrupt requests; and

a plurality of processor cores coupled to the interrupt logic;

wherein the data structure comprises a plurality of entries, each entry corresponding to a different interrupt request and having multiple fields;

wherein the interrupt logic receives an interrupt request and selectively transfers the interrupt request to a single processor core selected from the plurality of processor cores as indicated by a first field of an entry corresponding to said interrupt request;

wherein said one of the plurality of processor cores services the interrupt request.

2. The system of claim 1, wherein said single processor core services the interrupt request by executing interrupt service routine instructions, a location of said interrupt service routine instructions indicated in a second field of said entry corresponding to said interrupt request.

3. The system of claim 1, wherein the system is selected from the group consisting of a battery-operated device or a mobile communication device.

4. The system of claim 1, wherein the entry corresponding to said interrupt request further comprises a second field that is indicative of a status of the interrupt request.

5. The system of claim 4, wherein, upon servicing the interrupt request, said single processor core transfers an acknowledgement signal to the interrupt logic.

6. The system of claim 5, wherein the interrupt logic, upon receiving the acknowledgement signal, modifies the second field.

7. The system of claim 4, wherein the interrupt logic transfers the interrupt request to said single processor core if indicated by said second field.

8. The system of claim 1, wherein said single processor core services a portion of the interrupt request and another processor core services a different portion of the interrupt request.

9. An electronic device, comprising:

a data structure including a plurality of entries, at least one entry corresponding to an interrupt request and comprising a first field and a second field;

wherein the electronic device receives the interrupt request and selectively transfers the interrupt request to a single processor selected from a plurality of processors as indicated by contents of the first field;

wherein the single processor retrieves a group of instructions from a memory location specified by the second field;

wherein, when executed, the group of instructions causes the single processor to pause execution of a thread, to service the interrupt request, and to resume execution of the thread.

10. The electronic device of claim 9, wherein the at least one entry further comprises a third field that indicates a status of the corresponding interrupt service request.

11. The electronic device of claim 9, wherein the electronic device receives an acknowledgement signal from said single processor indicating that said single processor has serviced the interrupt request.

12. The electronic device of claim 11, wherein the electronic device modifies contents of a third field of the entry upon receiving said acknowledgement signal.

13. The electronic device of claim 9, wherein the single processor services the interrupt request in part, and another one of the plurality of processors finishes servicing the interrupt request.

14. The electronic device of claim 9, wherein the electronic device is at least one of a battery-operated device or a mobile communication device.

15. A method, comprising:

transferring multiple interrupt requests to an interrupt logic comprising a data structure, at least some of the multiple interrupt requests inserted into the data structure;

selecting a particular interrupt request from among the multiple interrupt requests, said particular interrupt request corresponding to multiple fields;

interrupting a single processor selected from a plurality of processors as indicated by a first field of the particular interrupt request;

servicing said particular interrupt request on said single processor; and

transferring an acknowledgement signal to the interrupt logic upon servicing said particular interrupt request.

16. The method of claim 15, wherein servicing said particular interrupt request comprises locating instructions corresponding to said particular interrupt request using a second field of the particular interrupt request.

17. The method of claim 15 further comprising modifying, upon receiving the acknowledgement signal, a second field of the particular interrupt request, said second field indicative of a completion status of the particular interrupt request.

18. The method of claim 15 further comprising servicing a portion of said particular interrupt request on another one of the plurality of processors.