Patents by Inventor Gerardo A. Delgadino

Gerardo A. Delgadino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10134600
    Abstract: A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, comprising flowing a stripping gas comprising oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. A SiN layer is selectively etched with respect to SiO and SiGe and Si.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 20, 2018
    Assignee: Lam Research Corporation
    Inventors: Leonid Romm, Alan Jensen, Xin Zhang, Gerardo Delgadino
  • Publication number: 20180269071
    Abstract: A method for selectively etching SiN with respect to SiO or SiGe or Si of a structure is provided comprising providing a plurality of cycles of atomic layer etching. Each cycle comprises a fluorinated polymer deposition phase comprising flowing a fluorinated polymer deposition gas comprising a hydrofluorocarbon gas into the plasma processing chamber, forming the fluorinated polymer deposition gas into a plasma, which deposits a hydrofluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas into the plasma processing chamber and an activation phase comprising flowing an activation gas comprising at least one of NH3 or H2 into the plasma processing chamber, forming the activation gas into a plasma, wherein plasma components from NH3 or H2 cause SiN to be selectively etched with respect to SiO or SiGe or Si, and stopping the flow of the activation gas into the plasma processing chamber.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Daniel LE, Gerardo DELGADINO
  • Patent number: 10079154
    Abstract: A method for selectively etching SiN with respect to SiO or SiGe or Si of a structure is provided comprising providing a plurality of cycles of atomic layer etching. Each cycle comprises a fluorinated polymer deposition phase comprising flowing a fluorinated polymer deposition gas comprising a hydrofluorocarbon gas into the plasma processing chamber, forming the fluorinated polymer deposition gas into a plasma, which deposits a hydrofluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas into the plasma processing chamber and an activation phase comprising flowing an activation gas comprising at least one of NH3 or H2 into the plasma processing chamber, forming the activation gas into a plasma, wherein plasma components from NH3 or H2 cause SiN to be selectively etched with respect to SiO or SiGe or Si, and stopping the flow of the activation gas into the plasma processing chamber.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 18, 2018
    Assignee: Lam Research Corporation
    Inventors: Daniel Le, Gerardo Delgadino
  • Publication number: 20180226260
    Abstract: A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, comprising flowing a stripping gas comprising oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. A SiN layer is selectively etched with respect to SiO and SiGe and Si.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Inventors: Leonid ROMM, Alan JENSEN, Xin ZHANG, Gerardo DELGADINO
  • Patent number: 9779956
    Abstract: A method for selectively etching SiO and SiN with respect to SiGe or Si of a structure is provided. A plurality of cycles of atomic layer etching is provided, where each cycle comprises a fluorinated polymer deposition phase and an activation phase. The fluorinated polymer deposition phase comprises flowing a fluorinated polymer deposition gas comprising a fluorocarbon gas, forming the fluorinated polymer deposition gas into a plasma, which deposits a fluorocarbon polymer layer on the structure, and stopping the flow of the fluorinated polymer deposition gas. The activation phase comprises flowing an activation gas comprising an inert bombardment gas and H2, forming the activation gas into a plasma, wherein the inert bombardment gas activates fluorine in the fluorinated polymer which with the plasma components from H2 cause SiO and SiN to be selectively etched with respect to SiGe and Si, and stopping the flow of the activation gas.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 3, 2017
    Assignee: Lam Research Corporation
    Inventors: Xin Zhang, Alan Jensen, Gerardo Delgadino, Daniel Le
  • Patent number: 9515156
    Abstract: A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: December 6, 2016
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Paul Raymond Besser, Bart van Schravendijk, Yoshie Kimura, Gerardo A. Delgadino, Harald Orkorn-Schmidt, Dengliang Yang
  • Publication number: 20160111515
    Abstract: A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the plurality of fins; depositing a sacrificial spacer around the dummy gate; depositing a first interlayer dielectric (ILD) layer around the sacrificial spacer; selectively etching the dummy polysilicon gate relative to the first ILD layer and the sacrificial spacer; depositing a replacement metal gate (RMG); etching a portion of the RMG to create a recess surrounded by the sacrificial spacer; and depositing a gate capping layer in the recess. The gate capping layer is at least partially surrounded by the sacrificial spacer and is made of silicon oxycarbide (SiOC).
    Type: Application
    Filed: October 15, 2015
    Publication date: April 21, 2016
    Inventors: Paul Raymond Besser, Bart van Schravendijk, Yoshie Kimura, Gerardo A. Delgadino, Harald Orkorn-Schmidt, Dengliang Yang
  • Patent number: 9263240
    Abstract: A system and method of plasma processing includes a plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric temperature control zones and a controller coupled to the plasma chamber.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: February 16, 2016
    Assignee: Lam Research Corporation
    Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Ryan Bise, Lumin Li, Sang Ki Nam, Jim Rogers, Eric Hudson, Gerardo Delgadino, Andrew D. Bailey, III, Mike Kellogg, Anthony de la Llera
  • Patent number: 9040430
    Abstract: A method for stripping an organic mask above a porous low-k dielectric film is provided. A steady state flow of a stripping gas, comprising CO2 and CH4 is provided. The stripping gas is formed into a plasma, wherein the plasma strips at least half the organic mask and protects the porous low-k dielectric film, for a duration of providing the steady state flow of the stripping gas.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 26, 2015
    Assignee: Lam Research Corporation
    Inventors: John M. Nagarah, Gerardo Delgadino
  • Publication number: 20150004797
    Abstract: A method for stripping an organic mask above a porous low-k dielectric film is provided. A steady state flow of a stripping gas, comprising CO2 and CH4 is provided. The stripping gas is formed into a plasma, wherein the plasma strips at least half the organic mask and protects the porous low-k dielectric film, for a duration of providing the steady state flow of the stripping gas.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: John M. NAGARAH, Gerardo DELGADINO
  • Patent number: 8652298
    Abstract: Methods, systems, and computer programs are presented for semiconductor manufacturing are provided. One wafer processing apparatus includes: a top electrode; a bottom electrode; a first radio frequency (RF) power source; a second RF power source; a third RF power source; a fourth RF power source; and a switch. The first, second, and third power sources are coupled to the bottom electrode. Further, the switch is operable to be in one of a first position or a second position, where the first position causes the top electrode to be connected to ground, and the second position causes the top electrode to be connected to the fourth RF power source.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 18, 2014
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Alexei Marakhtanov, Gerardo Delgadino, Eric Hudson, Bi Ming Yen, Andrew D. Bailey, III
  • Publication number: 20130126486
    Abstract: A system and method of plasma processing includes a plasma processing system including a plasma chamber and a controller coupled to the plasma chamber. The plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric gas injection zones.
    Type: Application
    Filed: April 3, 2012
    Publication date: May 23, 2013
    Inventors: Ryan Bise, Rajinder Dhindsa, Alexei Marakhtanov, Lumin Li, Sang Ki Naw, Jim Rogers, Eric Hudson, Gerardo Delgadino, Andrew D. Bailey, III, Mike Kellogg, Anthony Dela Llera, Darrell Ehrlich
  • Publication number: 20130126475
    Abstract: Methods, systems, and computer programs are presented for semiconductor manufacturing are provided. One wafer processing apparatus includes: a top electrode; a bottom electrode; a first radio frequency (RF) power source; a second RF power source; a third RF power source; a fourth RF power source; and a switch. The first, second, and third power sources are coupled to the bottom electrode. Further, the switch is operable to be in one of a first position or a second position, where the first position causes the top electrode to be connected to ground, and the second position causes the top electrode to be connected to the fourth RF power source.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Applicant: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Alexei Marakhtanov, Gerardo Delgadino, Eric Hudson, Bi Ming Yen, Andrew D. Bailey, III
  • Publication number: 20130126476
    Abstract: A system and method of plasma processing includes a plasma chamber including a substrate support and an upper electrode opposite the substrate support, the upper electrode having a plurality of concentric temperature control zones and a controller coupled to the plasma chamber.
    Type: Application
    Filed: March 15, 2012
    Publication date: May 23, 2013
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Alexei Marakhtanov, Rajinder Dhindsa, Ryan Bise, Lumin Li, Sang Ki Nam, Jim Rogers, Eric Hudson, Gerardo Delgadino, Andrew D. Bailey, III, Mike Kellogg, Anthony de la LIera
  • Patent number: 8394722
    Abstract: A method for controlling critical dimension (CD) of etch features in an etch layer disposed below a functionalized organic mask layer disposed below an intermediate mask layer, disposed below a patterned photoresist mask, which forms a stack is provided. The intermediate mask layer is opened by selectively etching the intermediate mask layer with respect to the patterned photoresist mask. The functionalized organic mask layer is opened. The functionalized organic mask layer opening comprises flowing an open gas comprising COS, forming a plasma, and stopping the flowing of the open gas. The etch layer is etched.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: March 12, 2013
    Assignee: Lam Research Corporation
    Inventors: Gerardo A. Delgadino, Robert C. Hefty
  • Patent number: 8236188
    Abstract: A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: August 7, 2012
    Assignee: Lam Research Corporation
    Inventors: Bing Ji, Kenji Takeshita, Andrew D. Bailey, III, Eric A. Hudson, Maryam Moravej, Stephen M. Sirard, Jungmin Ko, Daniel Le, Robert C. Hefty, Yu Cheng, Gerardo A. Delgadino, Bi-Ming Yen
  • Patent number: 8083963
    Abstract: A substrate is processed in a process chamber comprising a substrate support having a receiving surface for receiving a substrate so that a front surface of the substrate is exposed within the chamber. An energized process gas is used to process the front surface of the substrate. A peripheral edge of the backside surface of the substrate is cleaned by raising the substrate above the receiving surface of the substrate support to a raised position, and exposing the backside surface of the substrate to an energized cleaning gas.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: December 27, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Gerardo A. Delgadino, Indrajit Lahiri, Teh-Tien Su, Sy-Yuan Brian Shieh, Ashok Sinha
  • Patent number: 8048806
    Abstract: In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by inhibiting formation of a parasitic plasma during the process transition. In some implementations, a method is provided for processing a workpiece in plasma processing chamber, which includes inhibiting deviations from an expected etch-rate distribution by avoiding unstable plasma states during a process transition from one process step to another process step.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: November 1, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Michael C. Kutney, Daniel J. Hoffman, Gerardo A. Delgadino, Ezra R. Gold, Ashok Sinha, Xiaoye Zhao, Douglas H. Burns, Shawming Ma
  • Patent number: 7977245
    Abstract: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing H2 gas, fluorine containing gas, at least an insert gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: July 12, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Ying Xiao, Gerardo A. Delgadino, Karsten Schneider
  • Patent number: 7828987
    Abstract: In some implementations, a method is provided in a plasma reactor for etching a trench in an organic planarization layer of a resist structure comprising a photoresist mask structure over a hardmask masking the organic planarization layer. This may include introducing into the plasma reactor an etchant gas chemistry including N2, H2, and O2 and etching a masked organic planarization layer using a plasma formed from the etchant gas chemistry. This may include etching through the planarization layer to form a trench with a single etch step.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: November 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Jens Karsten Schneider, Ying Xiao, Gerardo A. Delgadino