Abstract: Methods for two step etching a BARC layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having vias filled with a BARC layer disposed on the substrate in an etch reactor, supplying a first gas mixture into the reactor to etch a first portion of the BARC layer filling in the vias, and supplying a second gas mixture comprising NH3 gas into the reactor to etch a second portion of the BARC layer disposed in the vias.

Abstract: A plasma etch process includes a plasma etch step performed with a photoresist mask on a workpiece using a polymerizing etch process gas that produces in the plasma polymerizing species which accumulate as a protective polymer layer on the surface of said photoresist mask during the etch step, the process including the following steps performed in the same chamber after the etch step and prior to removing the photoresist mask: (a) removing residue of the type including polymer material from chamber surfaces including a ceiling of said chamber, by coupling RF plasma source power into the chamber while coupling substantially no RF plasma bias power into the chamber, and introducing a hydrogen-containing gas into the chamber, until said residue is removed from the chamber surfaces; (b) removing the protective polymer layer from the surface of the photoresist mask, by coupling RF plasma bias power into the chamber while coupling substantially no RF plasma source power into the chamber, and introducing into the

Abstract: In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by inhibiting formation of a parasitic plasma during the process transition. In some implementations, a method is provided for processing a workpiece in plasma processing chamber, which includes inhibiting deviations from an expected etch-rate distribution by avoiding unstable plasma states during a process transition from one process step to another process step.

Abstract: In some implementations, a method is provided for inhibiting charge damage in a plasma processing chamber during a process transition from one process step to another process step, including performing a pre-transition compensation of at least one process parameter so as to inhibit charge damage from occurring during the process transition. In some implementations, a method is provided for inhibiting charge damage during a process transition from one process step to another process step, which includes changing at least one process parameter with a smooth non-linear transition. In some implementations, a method is provided which includes sequentially changing selected process parameters such that a plasma is able to stabilize after each change prior to changing a next selected process parameter.

Abstract: A method of fabricating a dual damascene interconnect structure uses a very high frequency high-density plasma and selectively controlled substrate bias for in-situ etching a trench above a via hole of the interconnect structure and a barrier layer between the via hole and underlying conductive layer.

Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: In at least some embodiments, the present invention is a plasma etching method which includes applying a gas mixture comprising CF4, N2 and Ar and forming a high density and low bombardment energy plasma. The high density and low bombardment energy plasma is formed by using high source and low bias power settings. The gas mixture can further include H2, NH3, a hydrofluorocarbon gas and/or a fluorocarbon gas. The hydrofluorocarbon gas can include CH2F2, CH3F; and/or CHF3. The fluorocarbon gas can include C4F8, C4F6 and/or C5F8.

Abstract: Certain embodiments include an etching method including providing an etch material, applying a gas mixture including hydrogen, forming a plasma, and etching the etch material. The etch material can include a low-k dielectric material. The gas mixture can include a hydrogen gas, a hydrogen-free fluorocarbon, and a nitrogen gas, and further include one or more of a hydrofluorocarbon gas, an inert gas, and/or a carbon monoxide gas. The hydrogen gas can be a diatomic hydrogen, a hydrocarbon, a silane and/or a fluorine-free hydrogen gas, including H2, CH4, C2H4, NH3, and/or H2O gases. The hydrogen-free fluorocarbon gas can be a CxFy gas (where x?1 and Y?1) and the hydrofluorocarbon gas can be a CxHyFz gas (where x?1, y?1 and z?1). The gas mixture can be free of oxygen. Embodiments can include reduced pressures, reduced hydrogen flow rates and one or more plasma frequencies.

Abstract: A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.

Abstract: A plasma reactor for processing a semiconductor wafer includes a side wall and an overhead ceiling defining a chamber, a workpiece support cathode within the chamber having a working surface facing the ceiling for supporting a semiconductor workpiece, process gas inlets for introducing a process gas into the chamber and an RF bias power generator having a bias power frequency. There is a bias power feed point at the working surface and an RF conductor is connected between the RF bias power generator and the bias power feed point at the working surface. A dielectric sleeve surrounds a portion of the RF conductor, the sleeve having an axial length along the RF conductor, a dielectric constant and an axial location along the RF conductor, the length, dielectric constant and location of the sleeve being such that the sleeve provides a reactance that enhances plasma ion density uniformity over the working surface.

Abstract: A method of fabricating a dual damascene interconnect structure uses a very high frequency high-density plasma and selectively controlled substrate bias for in-situ etching a trench above a via hole of the interconnect structure and a barrier layer between the via hole and underlying conductive layer.

Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocargon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.

Abstract: A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A plasma reactor for processing a semiconductor wafer includes a side wall and an overhead ceiling defining a chamber, a workpiece support cathode within the chamber having a working surface facing the ceiling for supporting a semiconductor workpiece, process gas inlets for introducing a process gas into the chamber and an RF bias power generator having a bias power frequency. There is a bias power feed point at the working surface and an RF conductor is connected between the RF bias power generator and the bias power feed point at the working surface. A dielectric sleeve surrounds a portion of the RF conductor, the sleeve having an axial length along the RF conductor, a dielectric constant and an axial location along the RF conductor, the length, dielectric constant and location of the sleeve being such that the sleeve provides a reactance that enhances plasma ion density uniformity over the working surface.

Abstract: An RF power applicator of the reactor includes inner and outer conductive radial spokes. The set of inner conductive spokes extends radially outwardly from and is electrically connected to the conductive post toward the conductive side wall. The set of outer conductive spokes extends radially inwardly toward the conductive post from and is electrically connected to the conductive side wall. In this way, the inner and outer sets of conductive spokes are electrically connected together, the combination of the inner and outer set of spokes with the conductive enclosure having a fundamental resonant frequency inversely proportional to the height of the conductive enclosure and the lengths of the inner and outer set of conductive spokes. An RF source power generator is coupled across the RF power applicator and has an RF frequency corresponding to the fundamental resonant frequency.

Abstract: The present invention provides a dielectric etch process with good etch rate, good selectivity with respect to photoresist mask, and much reduced striation as compared with conventional dielectric etching processes having comparable etch rate and selectivity. In one embodiment of the present invention, the dielectric layer is formed on a substrate with an underlying layer of another material and an overlying photoresist mask. A process for etching the dielectric layer comprises introducing a novel process gas into a process zone and maintaining a plasma of the process gas for a period of time. The process gas comprises a fluorocarbon gas, oxygen, a hydrogen-containing gas, and, optionally, an inert gas.

Abstract: An inductive antenna of a plasma reactor for processing a semiconductor wafer is connected to a radio frequency (RF) power source, and consists of a conductor arranged in successive loops that wind in opposing directions, adjacent pairs of the successive loops having facing portions in which current flow is parallel, the facing portions being sufficiently close to at least nearly share a common current path, whereby to form transitions across the facing portions between opposing magnetic polarizations.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber ceiling and a chamber side wall and a workpiece support pedestal within the chamber, a process gas conduit and gas distribution orifices facing the interior of the chamber and coupled to the process gas conduit, a conductive enclosure outside of the chamber and overlying the ceiling and having a conductive side wall with a bottom edge supported on the chamber ceiling and a conductive ceiling supported on a top edge of the conductive side wall, and a conductive post extending parallel with the conductive side wall from a center portion of the conductive ceiling toward the chamber ceiling. An RF power applicator of the reactor includes inner and outer conductive radial spokes. The set of inner conductive spokes extends radially outwardly from and is electrically connected to the conductive post toward the conductive side wall.