Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

Abstract: An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. In an example, an upper (e.g., n-channel) device and a lower (e.g., p-channel) device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where the upper device is located vertically above the lower device. According to some embodiments, an internal spacer structure extends between the nanoribbons of the upper device and the nanoribbons of the lower device along the vertical direction, where the spacer structure has a stepwise or an otherwise outwardly protruding profile as it extends between the nanoribbons of the upper device and the lower device. Accordingly, in one example, a gate structure formed around the nanoribbons of both the n-channel device and the p-channel device exhibits a greater width in the region between the nanoribbons of the n-channel device and the nanoribbons of the p-channel device.

Abstract: Transistor structures with source/drain contact metallization that includes an oxygen scavenging material. By incorporating the oxygen scavenging material, oxidation of a contact liner metallization that interfaces with semiconductor source/drain material may be reduced and a source/drain contact metallization structure may display improved stability.

Abstract: Integrated circuitry comprising transistors having different transistor threshold voltages (Vt). In some examples, a gate electrode of the transistors with different Vt may include only one workfunction metal. Another metal, such as a fill metal, may be deposited over the workfunction metal and provide a solid-state source of fluorine that will subsequently diffuse toward the channel region(s), entering the workfunction metal. As diffused, different concentrations of fluorine may remain with workfunction metals of different transistors, thereby altering their threshold voltages. Different amounts of fluorine may be allowed to diffuse into different transistor structures to provide a range of Vt suitable for integrated circuit topologies of different performance/power metrics.

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices utilizing a metal fill in an epi region of a stacked transistor configuration. In one example, an n-channel device and the p-channel device may both be GAA transistors each having any number of nanoribbons extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. A metal fill may be provided around the source or drain region of the bottom semiconductor device to provide a high contact area between the highly conductive metal fill and the epitaxial material of that source or drain region. Metal fill may also be used around the top source or drain region to further improve conductivity throughout both of the stacked source or drain regions.

Abstract: An apparatus provides NMOS and PMOS transistors having asymmetric stacks. The apparatus includes a first transistor and a second transistor on a base layer. The first transistor includes first channel regions that include a first element, a first gate region around the first channel regions, and a first source region and a first drain region at opposite ends of the first channel regions. The second transistor includes second channel regions that include a second element, a second gate region around the second channel regions, and a second source region and a second drain region at opposite ends of the second channel regions. The first channel regions are not coplanar with the second channel regions. In some scenarios, the number of first channel regions in the first transistor is unequal to the number of second channel regions in the second transistor.

Abstract: The surfaces of NMOS (n-type metal-oxide-semiconductor) transistor epitaxial source and drain regions are heavily doped with an n-type chalcogen (e.g., tellurium, selenium, sulfur) to overcome the limitations of low-ionization energy n-type dopants (e.g., phosphorous, arsenic, antimony) to free-electron concentrations due to Fermi-level pinning. The chalcogen can be introduced to the source or drain region surfaces by diffusion from a chalcogen-rich metal contact layer or by chemical vapor deposition processes in which a chalcogen precursor flows over the source and drain regions after they are formed. In some embodiments, the chemical vapor deposition process can comprise silicon and chalcogen precursors flowing over the source and drain region surfaces to form a thin layer of silicon highly doped with a chalcogen.

Abstract: Outdiffusion of germanium from silicon-germanium source and drain regions of PMOS (p-channel metal-oxide-semiconductor) field effect transistors into metal contact layers located on the PMOS source and drain regions can reduce the concentration of germanium layer in the silicon-germanium in the vicinity of the silicon-germanium layer-metal contact layer interface. This region of reduced germanium concentration can increase the parasitic contact resistance, which can have a deleterious effect on PMOS transistor performance. Adding germanium to the metal contact layers can reduce or eliminate germanium outdiffusion and prevent parasitic contact resistance increases.

Abstract: Semiconductor devices and systems with liner-last trench contacts, and methods of forming the same. The semiconductor device comprises a source region and a drain region, a source trench contact coupled to the source region, and a drain trench contact coupled to the drain region. Each trench contact resides in a contact trench and includes a contact plug, a contact metal layer below the contact plug, and a trench liner at the sidewalls of the contact trench. The uppermost surface of the contact metal layer is below the lowermost surface of the trench liner. A channel couples the source region to the drain region, and a gate couples to the channel. The trench liner includes silicon and at least one of oxygen and carbon. The device may correspond to a nanoribbon transistor, a gate-all-around (GAA) transistor, a fin field-effect transistor (FinFET), a planar transistor, or a two-dimensional transistor.

Abstract: Technologies for strain engineering in gate-all-around (GAA) field-effect transistors (FETs) are disclosed. In an illustrative embodiment, the source/drain contacts for N-type metal-oxide-semiconductor (NMOS) FETs extend deeper into the source/drain regions than the source/drain contacts for P-type metal-oxide-semiconductor (PMOS) FETs. The source/drain contacts for the NMOS FETs may cause a tensile strain in the channel of the NMOS FETs, while the source/drain region of the PMOS FETS may cause a compressive strain in the channel of the PMOS FETs. The tensile and compressive strains on the NMOS and PMOS channels, respectively, can increase the speed of the NMOS and PMOS transistors.

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Abstract: Integrated circuit structures having varied percentage-Ge silicon germanium nanowires, and methods of fabricating integrated circuit structures having varied percentage-Ge silicon germanium nanowires, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A lower one of the horizontal nanowires has a relatively higher percentage-Ge silicon and germanium composition. An upper one of the horizontal nanowires has a relatively lower percentage-Ge silicon and germanium composition. An intermediate horizontal nanowire is vertically between the lower one of the horizontal nanowires and the upper one of the horizontal nanowires and has an intermediate percentage-Ge silicon and germanium composition between the relatively higher percentage-Ge silicon and germanium composition and the relatively lower percentage-Ge silicon and germanium composition. A gate structure is vertically around the stack of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having a heterogeneous or mixed cFET architecture are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, the first vertical stack of horizontal nanowires including (110) silicon nanowires, and the second vertical stack of horizontal nanowires including (100) silicon nanowires, or the first vertical stack of horizontal nanowires including (100) silicon nanowires, and the second vertical stack of horizontal nanowires including (110) silicon nanowires. First epitaxial source or drain structures are at ends of the first vertical stack of horizontal nanowires. Second epitaxial source or drain structures are at ends of the second vertical stack of horizontal nanowires, the second epitaxial source or drain structures vertically beneath and having a different composition than the first epitaxial source or drain structures.

Abstract: Architectures and methods for differential CMOS contact profiles. Architectures include a CMOS isolation layer with a plurality of negative metal oxide semiconductor (NMOS) regions and a plurality of positive metal oxide semiconductor (PMOS) regions. The NMOS regions have a respective NMOS contact characterized by a first cavity formed in an upper surface of the isolation layer, extending orthogonally into the NMOS region to a first depth, and filled with a conductive material. The PMOS regions have a respective PMOS contact characterized by a second cavity formed in the upper surface of the isolation layer, extending orthogonally into the PMOS region to a second depth, and filled with the conductive material. The first depth is more than four times the second depth.

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: Jumper gates for advanced integrated circuit structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowire segments. A second vertical stack of horizontal nanowire segments is spaced apart from the first vertical stack of horizontal nanowire segments. A conductive structure is laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments. A first source or drain structure is coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure. A second source or drain structure is coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) titanium silicide conductive contact material on the second pEPI region.