Abstract: An apparatus provides NMOS and PMOS transistors having asymmetric stacks. The apparatus includes a first transistor and a second transistor on a base layer. The first transistor includes first channel regions that include a first element, a first gate region around the first channel regions, and a first source region and a first drain region at opposite ends of the first channel regions. The second transistor includes second channel regions that include a second element, a second gate region around the second channel regions, and a second source region and a second drain region at opposite ends of the second channel regions. The first channel regions are not coplanar with the second channel regions. In some scenarios, the number of first channel regions in the first transistor is unequal to the number of second channel regions in the second transistor.

Abstract: The surfaces of NMOS (n-type metal-oxide-semiconductor) transistor epitaxial source and drain regions are heavily doped with an n-type chalcogen (e.g., tellurium, selenium, sulfur) to overcome the limitations of low-ionization energy n-type dopants (e.g., phosphorous, arsenic, antimony) to free-electron concentrations due to Fermi-level pinning. The chalcogen can be introduced to the source or drain region surfaces by diffusion from a chalcogen-rich metal contact layer or by chemical vapor deposition processes in which a chalcogen precursor flows over the source and drain regions after they are formed. In some embodiments, the chemical vapor deposition process can comprise silicon and chalcogen precursors flowing over the source and drain region surfaces to form a thin layer of silicon highly doped with a chalcogen.

Abstract: Outdiffusion of germanium from silicon-germanium source and drain regions of PMOS (p-channel metal-oxide-semiconductor) field effect transistors into metal contact layers located on the PMOS source and drain regions can reduce the concentration of germanium layer in the silicon-germanium in the vicinity of the silicon-germanium layer-metal contact layer interface. This region of reduced germanium concentration can increase the parasitic contact resistance, which can have a deleterious effect on PMOS transistor performance. Adding germanium to the metal contact layers can reduce or eliminate germanium outdiffusion and prevent parasitic contact resistance increases.

Abstract: Semiconductor devices and systems with liner-last trench contacts, and methods of forming the same. The semiconductor device comprises a source region and a drain region, a source trench contact coupled to the source region, and a drain trench contact coupled to the drain region. Each trench contact resides in a contact trench and includes a contact plug, a contact metal layer below the contact plug, and a trench liner at the sidewalls of the contact trench. The uppermost surface of the contact metal layer is below the lowermost surface of the trench liner. A channel couples the source region to the drain region, and a gate couples to the channel. The trench liner includes silicon and at least one of oxygen and carbon. The device may correspond to a nanoribbon transistor, a gate-all-around (GAA) transistor, a fin field-effect transistor (FinFET), a planar transistor, or a two-dimensional transistor.

Abstract: Technologies for strain engineering in gate-all-around (GAA) field-effect transistors (FETs) are disclosed. In an illustrative embodiment, the source/drain contacts for N-type metal-oxide-semiconductor (NMOS) FETs extend deeper into the source/drain regions than the source/drain contacts for P-type metal-oxide-semiconductor (PMOS) FETs. The source/drain contacts for the NMOS FETs may cause a tensile strain in the channel of the NMOS FETs, while the source/drain region of the PMOS FETS may cause a compressive strain in the channel of the PMOS FETs. The tensile and compressive strains on the NMOS and PMOS channels, respectively, can increase the speed of the NMOS and PMOS transistors.

Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.

Abstract: Integrated circuit structures having varied percentage-Ge silicon germanium nanowires, and methods of fabricating integrated circuit structures having varied percentage-Ge silicon germanium nanowires, are described. For example, an integrated circuit structure includes a stack of horizontal nanowires. A lower one of the horizontal nanowires has a relatively higher percentage-Ge silicon and germanium composition. An upper one of the horizontal nanowires has a relatively lower percentage-Ge silicon and germanium composition. An intermediate horizontal nanowire is vertically between the lower one of the horizontal nanowires and the upper one of the horizontal nanowires and has an intermediate percentage-Ge silicon and germanium composition between the relatively higher percentage-Ge silicon and germanium composition and the relatively lower percentage-Ge silicon and germanium composition. A gate structure is vertically around the stack of horizontal nanowires.

Abstract: Gate-all-around integrated circuit structures having a heterogeneous or mixed cFET architecture are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, the first vertical stack of horizontal nanowires including (110) silicon nanowires, and the second vertical stack of horizontal nanowires including (100) silicon nanowires, or the first vertical stack of horizontal nanowires including (100) silicon nanowires, and the second vertical stack of horizontal nanowires including (110) silicon nanowires. First epitaxial source or drain structures are at ends of the first vertical stack of horizontal nanowires. Second epitaxial source or drain structures are at ends of the second vertical stack of horizontal nanowires, the second epitaxial source or drain structures vertically beneath and having a different composition than the first epitaxial source or drain structures.

Abstract: Architectures and methods for differential CMOS contact profiles. Architectures include a CMOS isolation layer with a plurality of negative metal oxide semiconductor (NMOS) regions and a plurality of positive metal oxide semiconductor (PMOS) regions. The NMOS regions have a respective NMOS contact characterized by a first cavity formed in an upper surface of the isolation layer, extending orthogonally into the NMOS region to a first depth, and filled with a conductive material. The PMOS regions have a respective PMOS contact characterized by a second cavity formed in the upper surface of the isolation layer, extending orthogonally into the PMOS region to a second depth, and filled with the conductive material. The first depth is more than four times the second depth.

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: Jumper gates for advanced integrated circuit structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowire segments. A second vertical stack of horizontal nanowire segments is spaced apart from the first vertical stack of horizontal nanowire segments. A conductive structure is laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments. A first source or drain structure is coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure. A second source or drain structure is coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) titanium silicide conductive contact material on the second pEPI region.

Abstract: Integrated circuit structures having patterned nanowire thickness scaling are described. For example, a structure includes a first device of a device type including a first vertical arrangement of horizontal nanowires, and a first gate stack having a first conductive layer over a first gate dielectric layer. A second device of the device type includes a second vertical arrangement of horizontal nanowires laterally spaced apart from the first vertical arrangement of horizontal nanowires, and a second gate stack having a second conductive layer over a second gate dielectric layer. Each of the nanowires of the second vertical arrangement of nanowires has a vertical thickness less than a vertical thickness of each of the nanowires of the first vertical arrangement of horizontal nanowires. The nanowires of the second vertical arrangement of nanowires have a vertical spacing greater than a vertical spacing of the nanowires of the first vertical arrangement of horizontal nanowires.

Abstract: Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of making such devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first interface material over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type that is opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, and a second interface material over the second source region and the second drain region.

Abstract: Techniques are provided herein to form semiconductor devices having a frontside and backside contact in an epi region of a stacked transistor configuration. In one example, an n-channel device and a p-channel device may both be GAA transistors where the n-channel device is located vertically above the p-channel device (or vice versa). Source or drain regions are adjacent to both ends of the n-channel device and the p-channel device. Deep and narrow contacts may be formed from both the frontside and the backside of the integrated circuit through the stacked source or drain regions. The contacts may physically contact each other to form a combined contact that extends through an entirety of the stacked source or drain regions. The higher contact area provided to both source or drain regions provides a more robust ohmic contact with a lower contact resistance compared to previous contact architectures.

Abstract: Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) a capping layer comprising silicon over the second pEPI region. A conductive contact material comprising titanium is on the capping layer.

Abstract: An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

Abstract: Contact over active gate (COAG) structures with trench contact layers, and methods of fabricating contact over active gate (COAG) structures using trench contact layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is adjacent to the gate structure. A conductive trench contact structure is on the epitaxial source or drain structure. The conductive trench contact structure includes a first planar layer on the epitaxial source or drain structure, a second planar layer on the first planar layer, and a conductive fill material on the second planar layer.

Abstract: Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.

Abstract: Techniques are provided herein to form semiconductor devices having strained channel regions. In an example, semiconductor nanoribbons of silicon germanium (SiGe) or germanium tin (GeSn) may be formed and subsequently annealed to drive the germanium or tin inwards along a portion of the semiconductor nanoribbons thus increasing the germanium or tin concentration through a central portion along the lengths of the one or more nanoribbons. Specifically, a nanoribbon may have a first region at one end of the nanoribbon having a first germanium concentration, a second region at the other end of the nanoribbon having substantially the same first germanium concentration (e.g., within 5%), and a third region between the first and second regions having a second germanium concentration higher than the first concentration. A similar material gradient may also be created using tin. The change in material composition (gradient) along the nanoribbon length imparts a compressive strain.