Patents by Inventor Gilbert Dewey

Gilbert Dewey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031503
    Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
  • Patent number: 11031482
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. Vacancies in the gate dielectric layer may be filled with capping layer material.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Publication number: 20210167216
    Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 11017843
    Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 25, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek Sharma, Gilbert Dewey, Willy Rachmady, Van Le, Matthew Metz, Jack Kavalieros
  • Patent number: 11011550
    Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Van Le, Abhishek Sharma, Gilbert Dewey, Ravi Pillarisetty, Shriram Shivaraman, Tahir Ghani, Jack Kavalieros
  • Publication number: 20210091080
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).
    Type: Application
    Filed: March 28, 2018
    Publication date: March 25, 2021
    Inventors: Gilbert DEWEY, Ravi PILLARISETTY, Abhishek A. SHARMA, Aaron D. LILAK, Willy RACHMADY, Rishabh MEHANDRU, Kimin JUN, Anh PHAN, Hui Jae YOO, Patrick MORROW, Cheng-Ying HUANG
  • Patent number: 10957769
    Abstract: Monolithic FETs including a fin of a first III-V semiconductor material offering high carrier mobility is clad with a second III-V semiconductor material having a wider bandgap. The wider bandgap cladding may advantageously reduce band-to-band tunneling (BTBT) leakage current while transistor is in an off-state while the lower bandgap core material may advantageously provide high current conduction while transistor is in an on-state. In some embodiments, a InGaAs cladding material richer in Ga is grown over an InGaAs core material richer in In. In some embodiments, the semiconductor cladding is a few nanometers thick layer epitaxially grown on surfaces of the semiconductor core. The cladded fin may be further integrated into a gate-last finFET fabrication process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Chandra S. Mohapatra, Gilbert Dewey, Willy Rachmady, Harold W. Kennel, Matthew V. Metz, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10950733
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 16, 2021
    Assignee: Google LLC
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Publication number: 20210074702
    Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 11, 2021
    Applicant: Intel Corporation
    Inventors: Van H. Le, Marko Radosavljevic, Han Wui Then, Willy Rachmady, Ravi Pillarisetty, Abhishek Sharma, Gilbert Dewey, Sansaptak Dasgupta
  • Publication number: 20210074828
    Abstract: An embodiment includes a system comprising: a switching device that includes a fin; and a source contact on a source, a gate contact on a channel, and a drain contact on a drain; wherein the gate contact includes: (a)(i) a first layer that includes oxygen, the first layer directly contacting the fin, (a)(ii) a second layer that includes a dielectric material, (c) a third layer that includes at least one of aluminum, titanium, ruthenium, zirconium, hafnium, tantalum, niobium, vanadium, thorium, barium, magnesium, cerium, and lanthanum, and (a)(iii) a fourth layer that includes a metal, wherein (b)(i) the source contact, the gate contact, and the drain contact are all on the fin, and (b)(ii) the second layer is between the first and fourth layers. Other embodiments are described herein.
    Type: Application
    Filed: December 26, 2017
    Publication date: March 11, 2021
    Inventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
  • Publication number: 20210074703
    Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.
    Type: Application
    Filed: March 22, 2018
    Publication date: March 11, 2021
    Inventors: Cory E. WEBER, Haorld W. KENNEL, Willy RACHMADY, Gilbert DEWEY
  • Publication number: 20210074704
    Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.
    Type: Application
    Filed: January 10, 2018
    Publication date: March 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Patrick Morrow, Rishabh Mehandru
  • Publication number: 20210057413
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.
    Type: Application
    Filed: March 28, 2018
    Publication date: February 25, 2021
    Inventors: Gilbert DEWEY, Ravi PILLARISETTY, Jack T. KAVALIEROS, Aaron D. LILAK, Willy RACHMADY, Rishabh MEHANDRU, Kimin JUN, Anh PHAN, Hui Jae YOO, Patrick MORROW, Cheng-Ying HUANG, Matthew V. METZ
  • Patent number: 10930791
    Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in a source/drain for low access and contact resistance of thin film transistors.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Van H. Le, Rafael Rios, Shriram Shivaraman, Jack T. Kavalieros, Marko Radosavljevic
  • Patent number: 10930679
    Abstract: Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek A. Sharma, Shriram Shivaraman, Van H. Le, Ravi Pillarisetty, Tahir Ghani
  • Publication number: 20210050455
    Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 18, 2021
    Inventors: Van H. LE, Gilbert DEWEY, Rafael RIOS, Jack T. KAVALIEROS, Marko RADOSAVLJEVIC, Kent E. MILLARD, Marc C. FRENCH, Ashish AGRAWAL, Benjamin CHU-KUNG, Ryan E. ARCH
  • Publication number: 20210036023
    Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Ashish Agrawal, Jack Kavalieros, Anand Murthy, Gilbert Dewey, Matthew Metz, Willy Rachmady, Cheng-Ying Huang, Cory Bomberger
  • Patent number: 10903364
    Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Sanaz K. Gardner, Chandra S. Mohapatra, Matthew V. Metz, Gilbert Dewey, Sean T. Ma, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • Patent number: 10886408
    Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 5, 2021
    Assignee: INTEL CORPORATION
    Inventors: Chandra S. Mohapatra, Harold W. Kennel, Glenn A. Glass, Willy Rachmady, Anand S. Murthy, Gilbert Dewey, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz, Sean T. Ma
  • Publication number: 20200411692
    Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber