Patents by Inventor Gilbert Dewey
Gilbert Dewey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923410Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).Type: GrantFiled: October 4, 2021Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
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Patent number: 11923290Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.Type: GrantFiled: June 26, 2020Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Siddharth Chouksey, Gilbert Dewey, Nazila Haratipour, Mengcheng Lu, Jitendra Kumar Jha, Jack T. Kavalieros, Matthew V. Metz, Scott B Clendenning, Eric Charles Mattson
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Patent number: 11916118Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.Type: GrantFiled: April 4, 2023Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
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Publication number: 20240055531Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.Type: ApplicationFiled: October 25, 2023Publication date: February 15, 2024Applicant: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
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Publication number: 20240047559Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Inventors: Willy RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Patrick MORROW, Anh PHAN, Cheng-Ying HUANG, Ehren MANNEBACH
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Patent number: 11895824Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.Type: GrantFiled: February 8, 2022Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Gilbert Dewey, Abhishek A Sharma
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Patent number: 11894465Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.Type: GrantFiled: February 12, 2021Date of Patent: February 6, 2024Assignee: Google LLCInventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
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Patent number: 11894372Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.Type: GrantFiled: January 11, 2023Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron Lilak, Patrick Morrow, Anh Phan, Ehren Mannebach, Jack T. Kavalieros
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Patent number: 11887988Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.Type: GrantFiled: August 1, 2019Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Ashish Agrawal, Jack Kavalieros, Anand Murthy, Gilbert Dewey, Matthew Metz, Willy Rachmady, Cheng-Ying Huang, Cory Bomberger
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Patent number: 11869894Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.Type: GrantFiled: July 13, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Aaron D. Lilak, Anh Phan, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres, Kimin Jun, Tristan A. Tronic, Christopher J. Jezewski, Hui Jae Yoo, Robert S. Chau, Chi-Hwa Tsang
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Patent number: 11869890Abstract: An apparatus is provided which comprises: a first transistor comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor, a second transistor comprising a source region and a drain region with a channel region therebetween, wherein the second transistor is over the first dielectric layer, a second dielectric layer over the second transistor, and a contact coupled to the source region or the drain region of the first transistor, wherein the contact comprises a metal having a straight sidewall that extends from through both the first and second dielectric layers. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 26, 2017Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Ravi Pillarisetty, Willy Rachmady, Gilbert Dewey, Rishabh Mehandru, Jack T. Kavalieros
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Publication number: 20240006494Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
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Publication number: 20240006506Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.Type: ApplicationFiled: July 2, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Gilbert Dewey, Siddharth Chouksey, Nazila Haratipour, Christopher Jezewski, Jitendra Kumar Jha, Ilya V. Karpov, Jack T. Kavalieros, Arnab Sen Gupta, I-Cheng Tung, Nancy Zelick, Chi-Hing Choi, Dan S. Lavric
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Publication number: 20240006533Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.Type: ApplicationFiled: July 2, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Gilbert Dewey, Siddharth Chouksey, Nazila Haratipour, Christopher Jezewski, Jitendra Kumar Jha, Ilya V. Karpov, Matthew V. Metz, Arnab Sen Gupta, I-Cheng Tung, Nancy Zelick, Chi-Hing Choi, Dan S. Lavric
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Publication number: 20240006488Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, David Kohen, Natalie Briggs, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
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Patent number: 11862728Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.Type: GrantFiled: October 1, 2021Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
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Patent number: 11862730Abstract: Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.Type: GrantFiled: May 27, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey
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Publication number: 20230420456Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Debaleena NANDI, Imola ZIGONEANU, Gilbert DEWEY, Anant H. JAHAGIRDAR, Harold W. KENNEL, Pratik PATEL, Anand S. MURTHY, Chi-Hing CHOI, Mauro J. KOBRINSKY, Tahir GHANI
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Publication number: 20230420246Abstract: An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. A region including metals and semiconductor materials is between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopants is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region, and wherein the section of the source or drain region is at a distance of at most 5 nanometers (nm) from the region.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Ilya V. Karpov, Aaron A. Budrevich, Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Dan S. Lavric
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Publication number: 20230420460Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Cheng-Ying Huang, Patrick Morrow, Quan Shi, Rohit Galatage, Nicole K. Thomas, Munzarin F. Qayyum, Jami A. Wiedemer, Gilbert Dewey, Mauro J. Kobrinsky, Marko Radosavljevic, Jack T. Kavalieros