Patents by Inventor Gill Yong Lee

Gill Yong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200286897
    Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 10, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
  • Publication number: 20200251151
    Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 6, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
  • Publication number: 20200235104
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Jianxin Lei, Wenting Hou, Mihaela Balseanu, Ning Li, Sanjay Natarajan, Gill Yong Lee, In Seok Hwang, Nobuyuki Sasaki, Sung-Kwan Kang
  • Patent number: 10700072
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Jianxin Lei, Wenting Hou, Mihaela Balseanu, Ning Li, Sanjay Natarajan, Gill Yong Lee, In Seok Hwang, Nobuyuki Sasaki, Sung-Kwan Kang
  • Publication number: 20200202900
    Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers include a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 25, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Sung-Kwan Kang, Gill Yong Lee, Chang Seok Kang
  • Publication number: 20200176451
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Sung-Kwan Kang, Gill Yong Lee, Sang Ho Yu, Shih Chung Chen, Jeffrey W. Anthis
  • Publication number: 20200126996
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 23, 2020
    Inventors: Priyadarshi Panda, Jianxin Lei, Wenting Hou, Mihaela Baiseanu, Ning Li, Sanjay Natarajan, Gill Yong Lee, In Seok Hwang, Nobuyuki Sasaki, Sung-Kwan Kang
  • Patent number: 9653311
    Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming stair-like structures on a substrate includes forming a film stack including a dielectric layer and a ruthenium containing material, and etching the ruthenium containing material in the film stack exposed by a patterned photoresist layer utilizing a first etching gas mixture comprising an oxygen containing gas.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: May 16, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Seul Ki Ahn, Seung-Young Son, Gill Yong Lee
  • Patent number: 8178379
    Abstract: According to one embodiment of the present invention, a memory device includes a composite structure including a resistivity changing layer and an electrode layer being arranged on or above the resistivity changing layer. The resistivity changing memory device further includes a protection layer being arranged on or above the composite structure, the protection layer protecting the electrode layer against electromagnetic waves.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: May 15, 2012
    Assignees: Qimonda AG, ALTIS Semiconductor, SNC
    Inventors: Philippe Blanchard, Gill Yong Lee
  • Patent number: 7682841
    Abstract: A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: March 23, 2010
    Assignees: Qimonda AG, Altis Semiconductor, SNC.
    Inventors: Faiz Dahmani, Gill Yong Lee
  • Publication number: 20090225580
    Abstract: An integrated circuit includes a plurality of memory cells, each memory cell including a memory element and a select device; and a plurality of word lines and bit lines connected to the memory cells. The bit lines, word lines, and the memory elements are arranged above the select devices.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 10, 2009
    Inventors: Peng-Fei Wang, Gill Yong Lee, Lothar Risch
  • Publication number: 20090218644
    Abstract: According to one embodiment of the present invention, an integrated circuit including a plurality of conductive lines is provided. The conductive lines are configured to guide electric currents or voltages. The conductive lines are at least partially surrounded by material which increases the electric field confinement of electric fields occurring within the conductive lines, and which functions as a diffusion barrier for material included within the conductive lines.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventor: Gill Yong Lee
  • Publication number: 20090072348
    Abstract: Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate, at least one first electrode disposed in or above the substrate, ion conductor doping material disposed above the at least one first electrode, ion conductor material disposed above the ion conductor doping material, and at least one second electrode disposed above the ion conductor material.
    Type: Application
    Filed: September 19, 2007
    Publication date: March 19, 2009
    Inventors: Ulrich Klostermann, Gill Yong Lee
  • Publication number: 20080274567
    Abstract: A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.
    Type: Application
    Filed: May 2, 2007
    Publication date: November 6, 2008
    Inventors: Faiz Dahmani, Gill Yong Lee
  • Publication number: 20080253168
    Abstract: According to one embodiment of the present invention, a memory device includes a composite structure including a resistivity changing layer and an electrode layer being arranged on or above the resistivity changing layer. The resistivity changing memory device further includes a protection layer being arranged on or above the composite structure, the protection layer protecting the electrode layer against electromagnetic waves.
    Type: Application
    Filed: April 13, 2007
    Publication date: October 16, 2008
    Inventors: Philippe Blanchard, Gill Yong Lee
  • Patent number: 7368299
    Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is formed using lift-off techniques. To form the cap layer, resist layers are deposited and patterned, and material layers are deposited over the resist layers. Portions of the material layers are removed when the resist is stripped.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: May 6, 2008
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Gill Yong Lee, Eugene O'Sullivan
  • Patent number: 7084079
    Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Conti, Daniel C. Edelstein, Gill Yong Lee
  • Patent number: 7075807
    Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: July 11, 2006
    Assignees: Infineon Technologies AG, Altis Semiconductor
    Inventors: Rainer Leuschner, Daniel Braun, Gill Yong Lee, Ulrich Klostermann
  • Publication number: 20060038211
    Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 23, 2006
    Inventors: Rainer Leuschner, Daniel Braun, Gill Yong Lee, Ulrich Klostermann
  • Patent number: 7001783
    Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: February 21, 2006
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Gregory Costrini, Frank Findeis, Gill Yong Lee, Chanro Park