Patents by Inventor Gill Yong Lee
Gill Yong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230146831Abstract: A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.Type: ApplicationFiled: September 4, 2022Publication date: May 11, 2023Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Gill Yong Lee, Fred Fishburn, Tomohiko Kitajima, Sung-Kwan Kang, Sony Varghese
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Patent number: 11621266Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.Type: GrantFiled: November 9, 2021Date of Patent: April 4, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
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Publication number: 20230096309Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.Type: ApplicationFiled: September 27, 2021Publication date: March 30, 2023Inventors: Chang Seok KANG, Tomohiko KITAJIMA, Sung-Kwan KANG, Fredrick FISHBURN, Gill Yong LEE, Nitin K. INGLE
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Publication number: 20230101155Abstract: A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.Type: ApplicationFiled: July 19, 2022Publication date: March 30, 2023Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Fred Fishburn, Tomohiko Kitajima, Sung-Kwan Kang, Sony Varghese, Gill Yong Lee
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Publication number: 20230040627Abstract: Described is a semiconductor memory device and methods of manufacture. The semiconductor memory device comprises a memory array comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting a select-gate-for-drain (SGD) transistor to a strapping line.Type: ApplicationFiled: August 2, 2022Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sung-Kwan Kang
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Publication number: 20230012819Abstract: Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.Type: ApplicationFiled: July 8, 2022Publication date: January 19, 2023Inventors: John Byron Tolle, Tomohiko Kitajima, Thomas John Kirschenheiter, Patricia M. Liu, Zuoming Zhu, Joe Margetis, Fredrick David Fishburn, Abdul Wahab Mohammed, Gill Yong Lee
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Patent number: 11552082Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.Type: GrantFiled: August 25, 2020Date of Patent: January 10, 2023Assignee: Applied Materials, Inc.Inventors: Sung-Kwan Kang, Gill Yong Lee, Sang Ho Yu, Shih Chung Chen, Jeffrey W. Anthis
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Publication number: 20220415651Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Applicant: Applied Materials, Inc.Inventors: Qixin Shen, Chuanxi Yang, Hang Yu, Deenesh Padhi, Gill Yong Lee, Sung-Kwan Kang, Abdul Wahab Mohammed, Hailing Liu
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Publication number: 20220367560Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described decrease the resistivity of word lines by forming word lines comprising low resistivity materials. The low resistivity material has a resistivity in a range of from 5 ??cm to 100 ??cm. Low resistivity materials may be formed by recessing the word line and selectively growing the low resistivity materials in the recessed portion of the word line. Alternatively, low resistivity materials may be formed by depositing a metal layer and silicidating the metal in the word line region and in the common source line region.Type: ApplicationFiled: May 11, 2022Publication date: November 17, 2022Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee
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Publication number: 20220352176Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.Type: ApplicationFiled: April 25, 2022Publication date: November 3, 2022Applicant: Applied Materials, Inc.Inventors: Sung-Kwan Kang, Fredrick Fishburn, Abdul Wahab Mohammed, Gill Yong Lee
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Publication number: 20220319601Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.Type: ApplicationFiled: March 28, 2022Publication date: October 6, 2022Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Qian Fu, Sung-Kwan Kang, Takehito Koshizawa, Fredrick Fishburn
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Publication number: 20220108728Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
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Patent number: 11295786Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: GrantFiled: February 3, 2020Date of Patent: April 5, 2022Assignee: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
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Publication number: 20220068935Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.Type: ApplicationFiled: November 9, 2021Publication date: March 3, 2022Applicant: Applied Materials, Inc.Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
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Patent number: 11171141Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.Type: GrantFiled: February 28, 2020Date of Patent: November 9, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
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Publication number: 20210272604Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers include a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Applicant: Applied Materials, Inc.Inventors: Sung-Kwan Kang, Gill Yong Lee, Chang Seok Kang
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Publication number: 20200388621Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.Type: ApplicationFiled: August 25, 2020Publication date: December 10, 2020Applicant: Applied Materials, Inc.Inventors: Sung-Kwan Kang, Gill Yong Lee, Sang Ho Yu, Shih Chung Chen, Jeffrey W. Anthis
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Patent number: 10790287Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.Type: GrantFiled: November 29, 2018Date of Patent: September 29, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Sung-Kwan Kang, Gill Yong Lee, Sang Ho Yu, Shih Chung Chen, Jeffrey W. Anthis
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Publication number: 20200286897Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.Type: ApplicationFiled: February 28, 2020Publication date: September 10, 2020Applicant: Applied Materials, Inc.Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
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Publication number: 20200251151Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.Type: ApplicationFiled: February 3, 2020Publication date: August 6, 2020Applicant: Applied Materials, Inc.Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu