Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is formed using lift-off techniques. To form the cap layer, resist layers are deposited and patterned, and material layers are deposited over the resist layers. Portions of the material layers are removed when the resist is stripped.

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.

Abstract: A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.

Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.

Abstract: A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).

Abstract: A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.

Abstract: A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.

Abstract: A method of fabricating a magnetic memory device and a magnetic memory device structure. A buffer insulating layer is deposited over the top surface of the conductive hard mask of a magnetic memory cell. The buffer insulating layer is left remaining over the conductive hard mask top surface while the various material layers of the device are patterned and etched. The buffer insulating layer prevents the conductive hard mask top surface from being damaged during plasma-containing processes.

Abstract: A method of fabricating a magnetic memory cell and an MRAM structure. A thin conductive hard is used to pattern a magnetic stack material layer. Conductive studs are fully landed on the top of the thin conductive hard mask, preventing the magnetic memory cells from being exposed subsequent etchant chemistries. The conductive studs provide a large process window for the upper level wiring trench formation, and also provide etch selectivity during the patterning of the upper level wiring.

Abstract: A material that is harder than silicon dioxide is used as a hard mask to pattern the soft layer of an MTJ stack of a magnetic memory device, which increases the process window for post-MTJ stack planarization. The soft layer hard mask material may comprise SiC, SiON, SiCN or SiN or another dielectric material having a Young's modulus greater than the Young's modulus of silicon dioxide. A hard fill dielectric material is also used as an insulating material over the hard mask used to pattern the soft layer. The fill dielectric material may also comprise SiC, SiON, SiCN or SiN or another dielectric material having a Young's modulus greater than the Young's modulus of silicon dioxide.

Abstract: A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).

Abstract: A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

Abstract: A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Abstract: A semiconductor device and method of forming a patterned conductive layer on a semiconductor substrate are provided so as to prevent fluorine substance outflow from a fluorinated silicate glass (FSG) layer thereon and simultaneously so as to suppress back reflection of light waves into a photoresist layer during photolithographic processing. The substrate is coated in turn with a conductive layer, a dielectric (e.g., silicon dioxide) liner, a FSG layer, a silicon oxynitride layer preventing fluorine substance outflow therethrough from the FSG layer and also forming an antireflective coating (ARC), and a photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the underlying silicon oxynitride layer. The uncovered pattern portions of the silicon oxynitride ARC layer and corresponding underlying portions of the FSG layer and dielectric liner are then removed, e.g., by a single dry etching step, to expose pattern portions of the conductive layer for metallization.

Abstract: There is disclosed the process of forming a gate conductor for a semiconductor device. The process begins with the step of providing a semiconductor substrate having a gate stack formed thereon, the gate stack including a sidewall. Dielectric spacers are formed on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer being of a doped glass material. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacers are then removed.