Abstract: An improved process for preparing nitrogen containing substrates selected from the group consisting of silicon oxynitride, silicon nitride and titanium nitride films and silicon dioxide cap films characterized by prevent resist contamination when used as dielectric anti-reflective coatings, using a high density plasma CVD system, comprising: providing a processing chamber holding a wafer in a vacuum sufficient to enable O.sub.2 to be used as an oxygen source without risk of explosion in a plasma generating region of the processing chamber; introducing a gaseous mixture selected from the group consisting of SiH.sub.4 /O.sub.2 /N.sub.2 or SiH.sub.4 /O.sub.2 /N.sub.2 /Ar into the processing chamber; and subjecting the processing chamber to a RF electrical signal of sufficient frequency to create a high density plasma in the plasma generating region of said processing chamber, whereby said wafer is processed by resulting high density plasma generated by said RF electrical signal.

Abstract: A hard etch mask comprising phosphorus doped silicate glass for reactive ion etching of a substrate to form trenches therein.

Abstract: A semiconductor device and method of forming a patterned conductive layer on a semiconductor substrate are provided so as to prevent fluorine substance outflow from a fluorinated silicate glass (FSG) layer thereon and simultaneously so as to suppress back reflection of light waves into a photoresist layer during photolithographic processing. The substrate is coated in turn with a conductive layer, a dielectric (e.g., silicon dioxide) liner, a FSG layer, a silicon oxynitride layer preventing fluorine substance outflow therethrough from the FSG layer and also forming an antireflective coating (ARC), and a photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the underlying silicon oxynitride layer. The uncovered pattern portions of the silicon oxynitride ARC layer and corresponding underlying portions of the FSG layer and dielectric liner are then removed, e.g., by a single dry etching step, to expose pattern portions of the conductive layer for metallization.

Abstract: Disclosed are metal fuse structures and methods for making the same. The method includes forming the fuse structure from a metallization layer. Depositing a bottom oxide layer, that is an HDP oxide, over the fuse structure that is formed from the metallization layer. Depositing a doped oxide layer over the base oxide layer. Depositing a top oxide layer over the doped oxide layer. Etching through the top oxide layer. Detecting an increased level of a dopant species that is emitted when the doped oxide layer begins to etch. The method further includes terminating the etching when the increased level of dopant species is detected. Wherein at least the bottom oxide layer remains over the fuse structure that is formed from the metallization layer.