Abstract: Described herein is a wavelength dispersive optical system (10). The system (10) comprises at least one optical input (12, 14, 16) for projecting an input optical beam comprising a plurality of individual wavelength components and at least one optical output (18) for receiving one or more output optical beams. The system (10) also includes a diffractive optical element (DOE) (1) including a substrate (2) and an array of physical diffraction elements (3).

Abstract: Disclosed is a system and method for determining a wear or operational characteristic regarding an apparatus. The method includes: determining a position data of at least a portion of the apparatus, by analysing two-dimensional image data from each of a plurality of image sensors located to capture image data of the apparatus, or part thereof, and calculating a physical or operational characteristic using the position data.

Abstract: A member for assembly with other members in an assembled condition to form an excavation bucket, the member forming at least part of one of the walls of the bucket when in its assembled condition, the member comprising a body having a forward edge; a rearward edge; opposite inner and outer surfaces that extend between the edges; a first portion of the member being thicker between its inner and outer surfaces than a second portion of the member, the first portion being disposed forward of the second portion.

Abstract: A processor module can include a circuit board, a first programmable circuitry coupled to the circuit board, wherein the first programmable circuitry is configurable to implement different physical circuits, and a processor configured to execute program code. The processor can be coupled to the circuit board and to the first programmable circuitry. The processor module also can include random access memory (RAM) devices coupled to the circuit board and electrically coupled to the first programmable circuitry. The RAM devices can be coupled to the first programmable circuitry to form parallel channels of the RAM devices. The processor module further can include an interface coupled to the circuit board and electrically coupled to the first programmable circuitry for coupling input and output between the first programmable circuitry and external circuitry.

Abstract: A member for assembly with other members in an assembled condition to form an excavation bucket, the member forming at least part of one of the walls of the bucket when in its assembled condition, the member comprising a body having a forward edge; a rearward edge; opposite inner and outer surfaces that extend between the edges; a first portion of the member being thicker between its inner and outer surfaces than a second portion of the member, the first portion being disposed forward of the second portion.

Abstract: A graphical user interface (GUI) used to program complex hardware elements is provided that allows a variety of files to be used to control subsequent content displayed by the GUI. The control includes dynamic updating of actual GUI elements, as well as rule checking based upon data entered into the GUI. Configuration, rule, and GUI files can be used to control the eventual programming of the complex hardware elements. Graphical metaphors are established to enable the viewing of performance information and using that information to control the programming of the complex hardware elements.

Abstract: A data storage system includes a first circuit board, a plurality of sockets coupled to the first circuit board, an connector coupled to each of the sockets for coupling each of the sockets to external circuitry, and a plurality of memory modules, each memory module disposed within one of the sockets. The memory module includes a circuit board, an integrated circuit device having configurable blocks, DRAM devices that form parallel channels of DRAM memory and flash memory devices that form parallel channels of flash memory. The memory module also includes an interface electrically coupled to the integrated circuit device for coupling input and output between the integrated circuit device and external circuitry.

Abstract: Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.

Abstract: Access is provided to user registers of a user design implemented on an integrated circuit (IC). A memory of the IC is initialized with instructions, and a portion of the programmable logic and interconnect resources of the IC is configured to implement an access interface, multiplexer logic, and the user design. A processor is coupled to the programmable logic and interconnect resources and executes the instructions from the memory. The processor receives from an external user interface, via the access interface, an access command. For a read command, the processor reads a value from an identified user register and transmits the value to the external user interface. For a write command, the processor writes a write value specified by the access command to the specified user register via the multiplexer logic. The processor and the user design are both coupled to write to the user registers via the multiplexer logic.

Abstract: A data storage system 400 includes a first circuit board 401, a plurality of sockets 402 coupled to the first circuit board 401, an connector 403 coupled to each of the sockets 402 for coupling each of the sockets 402 to external circuitry, and a plurality of memory modules 100, each memory module 100 disposed within one of the sockets 402. The memory module 100 includes a circuit board 101, an integrated circuit device 130 having configurable logic, DRAM devices 120-129 that form parallel channels of DRAM memory and flash memory devices 140-160 that form parallel channels of flash memory. The memory module 100 also includes an interface 170 electrically coupled to the integrated circuit device 130 for coupling input and output between the integrated circuit device 130 and external circuitry.

Abstract: Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The PMs can provide a histogram of the transactions usable to evaluate system performance. The PMs can provide a time line diagram of the transactions to show the specific order the transactions occurred. The PMs can be provided in a multi-port memory controller (MPMC) to monitor the speed of read and write transactions from the MPMC ports, and used to configure logic within the MPMC to maximize the rate of data flow.

Abstract: A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine can be provided in the BRAM of an FPGA, and can be used to provide control logic in a multi-port memory controller (MPMC). The MPMC with such a state machine can then connect to multiple different types of memory devices either simultaneously or separately.

Abstract: Various embodiments of the invention provide a method for transferring communication data through one or more pins of a programmable logic device (PLD). The PLD includes a configuration port that may be used to program programmable logic and interconnect resources of the PLD. The programmable logic and interconnect resources include the input/output blocks of the PLD. Portions of the communication data are sequentially transferring between certain pins of the PLD and certain input/output registers in one or more input/output blocks associated with the pins. A frame of configuration data including a portion of the communication data is transferred between the input/output registers and a frame register of the configuration port of the PLD. Formats are converted between the portion of the communication data and the frame of the configuration data in the frame register of the PLD.

Abstract: Method and apparatus for communicating data between a network transceiver and memory circuitry is described. In one example, a transmit peripheral includes a streaming interface configured to receive a communication sequence having data read from the memory circuitry. A receive peripheral includes a streaming interface configured to transmit a communication sequence having data to be written to the memory circuitry. Media access control (MAC) circuitry is configured to transmit the data read from the memory circuitry to the network transceiver, and receive the data to be written to the memory circuitry from the network transceiver.