Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic.blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: Described is a method of converting one representation of a circuit into another. For example, a first network representation adapted for use with an FPGA can be converted into a second network representation adapted for use in a mask-programmable gate array. The method begins with accessing the first network representation, such as a netlist, and identifying signal paths that might be sensitive to race conditions. Representations of delay elements are then inserted into each sensitive signal path. The timing of the modified network representation is then modeled by calculating the delays associated with each signal path. Any differences in the modeled delay values are minimized by modifying one or more of the inserted delay-element representations. In one embodiment, the inserted delay-element representations include stopper cells that maintain the nets to and/or from the delay-element representations.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. A database can be expanded as new reduced logic block models are created for configurable logic block models that were not in the database. Similarly, a database can be used for the input/output blocks and programmable switch matrices of an FPGA.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: An integrated-circuit using a routing ring is disclosed. The routing ring has an internal routing grid and an external routing gird. Logic circuits surrounded by the routing ring use the internal routing grid while logic circuits outside the routing ring use the external routing grid. The internal and external routing grids can use different pitches so that circuits outside the routing ring can be optimized to a first pitch. Similarly, logic circuits surrounded by the routing ring can be optimized to use a second pitch. In one embodiment, the routing ring includes a plurality of wires that connect the logic circuits surrounded by the routing ring to the logic circuits outside the routing ring.

Abstract: Method and circuits to create reduced field programmable gate arrays (RFPGA) from the configuration data of field programmable gate arrays (FPGA) are disclosed. The configurable elements of the FPGA are replaced with standard cell circuits that reproduce the functionality of the configured FPGA. Specifically, reduced logic blocks are derived from the configuration data of configurable logic blocks. Similarly, reduced input/output blocks and reduced matrices are derived from the configuration data for input/output blocks and programmable switch matrices of the FPGA, respectively. The reduced logic blocks are arranged in a similar layout to the original CLBs so that timing relationships remain similar in the RFPGA and FPGA. The actual timing of the RFPGA can be modified by increasing or decreasing the timing delay on various signal paths based on the FPGA design or additional timing constraints.

Abstract: The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The controlwise intelligence of the IDMAC is given specific knowledge of the structure of certain pieces of memory or hardware registers, (e.g. parameter blocks), used for Inter Process Communication. This specific knowledge can be imparted during the design phase of the IDMAC, or dynamically provided during its operation as system requirements dictate. The IDMAC achieves its DMA controlwise intelligence by understanding parameter blocks (PBs). The IDMAC reads the structure of the PB from memory directly, gets all of its PB parameters directly from memory, dereferencing as required, and then begins transferring data between the source and destination as instructed by the PB(s). Examples of PB parameters are source address, destination address, transfer length, and data intelligence opcode.

Abstract: A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

Abstract: Described is a method of using place-holding cells, or “stopper cells,” to force a place-and-route tool to route a selected signal path through a particular physical location on a semiconductor die. In one method, phantom blocks, created from the design specification, define the area, logic, timing, and the placement of input/output (I/O) ports for a number of custom blocks. These phantom blocks are combined with any standard blocks to create a high-level description of a desired circuit. Then, for each I/O port of the custom blocks, a place-holding cell, or “stopper cell,” is added to the description in the path defined between the I/O port and its source or destination. The stopper cells are then grouped with the associated custom blocks and the resulting collection of stopper cells and blocks are placed and routed. Completed custom blocks can then be substituted for respective phantom blocks after place and route. Stopper cells preserve complex routing during this substitution.

Abstract: A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided.

Abstract: The Intelligent DMA Controller (IDMAC) significantly reduces system latency by replacing one or more layers of software with hardware. The IDMAC uses controlwise and datawise intelligence. The controlwise intelligence of the IDMAC is given specific knowledge of the structure of certain pieces of memory or hardware registers, (e.g. parameter blocks), used for Inter Process Communication. This specific knowledge can be imparted during the design phase of the IDMAC, or dynamically provided during its operation as system requirements dictate. The IDMAC achieves its DMA controlwise intelligence by understanding parameter blocks (PBs). The IDMAC reads the structure of the PB from memory directly, gets all of its PB parameters directly from memory, dereferencing as required, and then begins transferring data between the source and destination as instructed by the PB(s). Examples of PB parameters are source address, destination address, transfer length, and data intelligence opcode.

Abstract: A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells.

Abstract: A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

Abstract: A method and apparatus for generating circuitry to initialize memory contained in an integrated circuit generated from a description for a programmable logic device is provided. The initialization bits in the bit stream used to program the programmable logic device are identified and extracted. Using these initialization bits and a set of selectable control circuitry options, initialization control logic is generated. Data initialization logic is also generated using the extracted initialization bits.

Abstract: A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided.

Abstract: One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simulation model of the PLD and back annotates the simulation model with timing characteristics from a target technology. The back annotation substitutes timing values in the PLD simulation model with timing values from the target technology to generate the new integrated circuit simulation model.

Abstract: A programmable IC is provided that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells.

Abstract: One embodiment of the invention allows a designer to quickly and efficiently obtain a simulation model for a new integrated circuit implementation of a circuit design from the PLD simulation model for that circuit design. The designer begins with the simulation model of the PLD and back annotates the simulation model with timing characteristics from a target technology. The back annotation substitutes timing values in the PLD simulation model with timing values from the target technology to generate the new integrated circuit simulation model.

Abstract: A configuration emulation circuit generates configuration signals to emulate a Programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.

Abstract: A method and apparatus for converting a programmable logic device representation of a circuit into a second representation of the circuit. A circuit design is first captured and converted into a first representation of the circuit design. The first representation is for programming a programmable logic device. A first part of the first representation is for programming a configurable element in the programmable logic device. The first part of the first representation is used as a set of parameters for a general model of the configurable element. The second representation of the circuit includes the parameterized general model of the configurable element.