Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.

Abstract: Transistor devices having an indium-containing ternary or greater III-V compound active channels, and processes for the fabrication of the same, may be formed that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium-containing ternary or greater III-V compound may be deposited in narrow trenches on a reconstructed upper surface of a sub-structure, which may result in a fin that has indium rich side surfaces and an indium rich bottom surface. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or greater III-V compound active channels.

Abstract: A replacement fin in a heterogeneous FinFET transistor in which source and drain regions are grown in corresponding trenches that extend into a sub-fin region. This depth of the epitaxial source/drain regions, in combination with the selected materials, can reduce off-state leakage while also keeping high defect density portions out of the active portions of the source and drain. In one embodiment, materials are selected for the source and drain regions that have an energy band offset from the material selected for the substrate. This band offset between the source/drain material can further reduce sub-fin leakage.

Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

Abstract: Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.

Abstract: Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

Abstract: Techniques are disclosed for fabricating semiconductor transistor devices configured with a sub-fin insulation layer that reduces parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with a transistor). The parasitic leakage is reduced by fabricating transistors with a sacrificial layer in a sub-fin region of the substrate below at least a channel region of the fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced, either in whole or in part, with a dielectric material. The dielectric material increases the electrical resistivity of the substrate between corresponding source and drain portions of the fin, thus reducing parasitic leakage.

Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.