Abstract: Provided is a system and method for confidential repository searching. The method executed on a first computing device and includes: receiving an encrypted query term from the second computing device; searching the encrypted data repository by determining one or more matches of the encrypted query term to data in the encrypted data repository; communicating the one or more matches to the second computing device; receiving associative data from the second computing device, the associative data associated with data in the encrypted data repository that is to be retrieved and associated with one of the one or more matches; retrieving the encrypted data in the encrypted data repository associated with the received associative data; and communicating the retrieved encrypted data to the second computing device.

Abstract: Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

Abstract: Remote terminals are configured to generate ciphertexts from plaintext polynomials. Each ciphertext corresponds to a plaintext polynomial bound to a message space of a polynomial-based fully homomorphic cryptographic scheme. At least one server is configured to receive ciphertexts via a network from the plurality of remote terminals. The server performs a multiplication operation and an addition operation on the ciphertexts to obtain resultant ciphertexts. The multiplication operation includes performing a bitwise decomposition function on a ciphertext to obtain a bitwise decomposed ciphertext. The bitwise decomposition function maps a multi-bit data type to a sequence of bits. The multiplication operation further includes performing matrix multiplication on the bitwise decomposed ciphertext and a data element belonging to a set of data elements. Message filters, data search engines, and other applications are discussed.

Abstract: Cryptographic processor chips, systems and associated methods are disclosed. In one embodiment, a cryptographic processor is disclosed. The cryptographic processor includes a first cryptographic processing module to perform a first logic operation. The first cryptographic processing module includes first input circuitry to receive ciphertext input symbols. A first pipeline stage performs a first operation on the ciphertext input symbols and generates a first stage output. On-chip memory temporarily stores the first stage output and feeds the first stage output to a second pipeline stage in a pipelined manner. The second pipeline stage is configured to perform a second operation on the first stage output in a pipelined manner with respect to the first pipeline stage.

Abstract: Provided is a system and method for confidential string-matching and confidential deep-packet inspection. The method includes: receiving encrypted ciphertexts from a first computing device; windowing a text corpus and applying a hash; performing binning and splitting on the corpus set of hashes; performing batching on the binned and split corpus set of hashes; determining match ciphertexts by evaluating a homomorphic encryption circuit between the encrypted ciphertexts and the batched corpus set of hashes; and communicating the match ciphertexts to the first computing device, the confidential string matching determinable by the first computing device by: decrypting the match ciphertexts, determining from the decryption output, if the hash value for each pattern window matches the hash value for any corpus windows and if the matched windows are adjacent in the corpus.

Abstract: Provided is a system and method for hybrid windowing for string-matching of input patterns to a corpus. The method including: establishing a first window size and a hash function; performing hashing on input patterns having a size within a given range using dynamic-sized windows to determine a dynamic-windowed hash set, the given range established using the first window size; performing hashing on input patterns having a size outside the given range using fixed-sized windows to determine a fixed-windowed hash set; combining the dynamic-windowed hash set and the fixed-windowed hash set to determine a combined hash set; and outputting the combined hash set for use in the confidential string-matching.

Abstract: Cryptographic processor chips, systems and associated methods are disclosed. In one embodiment, a cryptographic processor is disclosed. The cryptographic processor includes a first cryptographic processing module to perform a first logic operation. The first cryptographic processing module includes first input circuitry to receive ciphertext input symbols. A first pipeline stage performs a first operation on the ciphertext input symbols and generates a first stage output. On-chip memory temporarily stores the first stage output and feeds the first stage output to a second pipeline stage in a pipelined manner. The second pipeline stage is configured to perform a second operation on the first stage output in a pipelined manner with respect to the first pipeline stage.

Abstract: Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

Abstract: Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

Abstract: The present disclosure relates generally to homomorphic encryption, and specifically to using homomorphic encryption for secure information storage, transfer and computing. Described are systems for governing information transfers and systems for secure financial processing that include a hardware security module configured to generate a public key and a corresponding private key, homomorphically re-encrypt a set of confidential information into an encrypted information package, and make the encrypted information package available to be communicated.

Abstract: Systems, methods and devices for validating and performing operations on homomorphically encrypted data are described herein. The methods include securely transmitting and extracting information from encrypted data without fully decrypting the data. A data request may include an encrypted portion including a set of confidential data. One or more sets of encrypted comparison data may be then retrieved from a database in response to the data request. The encrypted set of confidential data from the data request is then compared with each set of encrypted comparison data using one or more homomorphic operations to determine which set of encrypted comparison data matches the encrypted set of confidential data. If there is a match, this validates the set of confidential data. An encrypted indicator is then generated indicating success or failure in validating the set of confidential data, which may then be forwarded to a party associated with the data request.

Abstract: Methods and systems for a complementary metal oxide semiconductor wireless power receiver may include a receiver chip with an inductor, a configurable capacitance, and a rectifier. The method may include receiving an RF signal utilizing the inductor, extracting a clock signal from the received RF signal, generating a DC voltage utilizing a rectifier circuit, sampling the DC voltage, and adjusting the configurable capacitance based on the sampled DC voltage. The rectifier circuit may include CMOS transistors and T-gate switches for coupling to the inductor. The T-gate switches may be controlled by the generated DC voltage. A signed based gradient-descent algorithm may be utilized to maximize the DC voltage. The DC voltage may be sampled utilizing a comparator powered by the DC voltage, which may adaptively configure the capacitance. The inductor may be shielded utilizing a floating shield. The DC voltage may be increased utilizing a voltage-boosting rectifier.

Abstract: Systems, methods and devices for validating and performing operations on homomorphically encrypted data are described herein. The methods include securely transmitting and extracting information from encrypted data without fully decrypting the data. A data request may include an encrypted portion including a set of confidential data. One or more sets of encrypted comparison data may be then retrieved from a database in response to the data request. The encrypted set of confidential data from the data request is then compared with each set of encrypted comparison data using one or more homomorphic operations to determine which set of encrypted comparison data matches the encrypted set of confidential data. If there is a match, this validates the set of confidential data. An encrypted indicator is then generated indicating success or failure in validating the set of confidential data, which may then be forwarded to a party associated with the data request.

Abstract: Provided is a system and method for confidential string-matching and confidential deep-packet inspection. The method includes: receiving encrypted ciphertexts from a first computing device; windowing a text corpus and applying a hash; performing binning and splitting on the corpus set of hashes; performing batching on the binned and split corpus set of hashes; determining match ciphertexts by evaluating a homomorphic encryption circuit between the encrypted ciphertexts and the batched corpus set of hashes; and communicating the match ciphertexts to the first computing device, the confidential string matching determinable by the first computing device by: decrypting the match ciphertexts, determining from the decryption output, if the hash value for each pattern window matches the hash value for any corpus windows and if the matched windows are adjacent in the corpus.

Abstract: Provided is a system and method for confidential string-matching and confidential deep-packet inspection. The method includes: receiving encrypted ciphertexts from a first computing device; windowing a text corpus and applying a hash; performing binning and splitting on the corpus set of hashes; performing batching on the binned and split corpus set of hashes; determining match ciphertexts by evaluating a homomorphic encryption circuit between the encrypted ciphertexts and the batched corpus set of hashes; and communicating the match ciphertexts to the first computing device, the confidential string matching determinable by the first computing device by: decrypting the match ciphertexts, determining from the decryption output, if the hash value for each pattern window matches the hash value for any corpus windows and if the matched windows are adjacent in the corpus.

Abstract: Methods and systems for a complementary metal oxide semiconductor wireless power receiver may include a receiver chip with an inductor, a configurable capacitance, and a rectifier. The method may include receiving an RF signal utilizing the inductor, extracting a clock signal from the received RF signal, generating a DC voltage utilizing a rectifier circuit, sampling the DC voltage, and adjusting the configurable capacitance based on the sampled DC voltage. The rectifier circuit may include CMOS transistors and T-gate switches for coupling to the inductor. The T-gate switches may be controlled by the generated DC voltage. A signed based gradient-descent algorithm may be utilized to maximize the DC voltage. The DC voltage may be sampled utilizing a comparator powered by the DC voltage, which may adaptively configure the capacitance. The inductor may be shielded utilizing a floating shield. The DC voltage may be increased utilizing a voltage-boosting rectifier.

Abstract: Disclosed are methods and systems for the detection of bacteria in a sample. The methods comprises contacting the sample with an antibacterial agent and a bacteria identification sensor, and involves the permeabilization of the bacteria by the antibacterial agent, and the subsequent detection of an efflux of potassium ions using a bacteria identification sensor comprising a potassium-sensitive ISFET. Also disclosed are bacteria identification sensor comprising a potassium-sensitive ISFET useful in the practice of the disclosed methods.

Abstract: Remote terminals are configured to generate ciphertexts from plaintext polynomials. Each ciphertext corresponds to a plaintext polynomial bound to a message space of a polynomial-based fully homomorphic cryptographic scheme. At least one server is configured to receive ciphertexts via a network from the plurality of remote terminals. The server performs a multiplication operation and an addition operation on the ciphertexts to obtain resultant ciphertexts. The multiplication operation includes performing a bitwise decomposition function on a ciphertext to obtain a bitwise decomposed ciphertext. The bitwise decomposition function maps a multi-bit data type to a sequence of bits. The multiplication operation further includes performing matrix multiplication on the bitwise decomposed ciphertext and a data element belonging to a set of data elements. Message filters, data search engines, and other applications are discussed.

Abstract: Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

Abstract: Methods and systems for a complementary metal oxide semiconductor wireless power receiver may include a receiver chip with an inductor, a configurable capacitance, and a rectifier. The method may include receiving an RF signal utilizing the inductor, extracting a clock signal from the received RF signal, generating a DC voltage utilizing a rectifier circuit, sampling the DC voltage, and adjusting the configurable capacitance based on the sampled DC voltage. The rectifier circuit may include CMOS transistors and T-gate switches for coupling to the inductor. The T-gate switches may be controlled by the generated DC voltage. A signed based gradient-descent algorithm may be utilized to maximize the DC voltage. The DC voltage may be sampled utilizing a comparator powered by the DC voltage, which may adaptively configure the capacitance. The inductor may be shielded utilizing a floating shield. The DC voltage may be increased utilizing a voltage-boosting rectifier.