Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract: A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

Abstract: A system and method of validating and performing operations on homomorphically encrypted data are described herein. The methods include processing a secure financial transaction by receiving a transaction request to complete a financial transaction, with at least a portion of the request encrypted according to a homomorphic encryption scheme, and the transaction request comprising confidential cardholder data including an account number, non-confidential cardholder data, and transaction data, and retrieving one or more sets of encrypted comparison cardholder data encrypted according to a homomorphic encryption scheme. The confidential cardholder data is then compared to each set of the comparison cardholder data using one or more homomorphic operations to determine which set of comparison cardholder data matches the confidential cardholder data and validating the confidential cardholder data.

Abstract: Methods and systems for a complementary metal oxide semiconductor wireless power receiver may include a receiver chip with an inductor, a configurable capacitance, and a rectifier. The method may include receiving an RF signal utilizing the inductor, extracting a clock signal from the received RF signal, generating a DC voltage utilizing a rectifier circuit, sampling the DC voltage, and adjusting the configurable capacitance based on the sampled DC voltage. The rectifier circuit may include CMOS transistors and T-gate switches for coupling to the inductor. The T-gate switches may be controlled by the generated DC voltage. A signed based gradient-descent algorithm may be utilized to maximize the DC voltage. The DC voltage may be sampled utilizing a comparator powered by the DC voltage, which may adaptively configure the capacitance. The inductor may be shielded utilizing a floating shield. The DC voltage may be increased utilizing a voltage-boosting rectifier.

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract: Methods and systems for maximum achievable efficiency in near-field coupled wireless power transfer systems may comprise, for example, configuring coil geometry for a transmit (Tx) coil and a receive (Rx) coil based on a media expected to be between the coils during operation. A desired susceptance and conductance may be determined and an impedance of an amplifier for the Tx coil may be configured based on the determined susceptance and conductance. A load impedance for the Rx coil may be configured based on the determined susceptance and conductance. A matching network may be coupled to the amplifier. The Rx coil may be integrated on a complementary metal-oxide semiconductor (CMOS) chip. One or more matching networks may be integrated on the CMOS chip for the configuring of the load impedance for the Rx coil.

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract: An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2NT?1 (NT=number of transmit antennas) on-demand to only 2K?1 lowest Partial Euclidean Distance (PED) paths at last tree level 2NT. The relaxed LLR computation scheme includes approximating LLR computations by assuming that discarded path PED is greater than or equal K-Best path PED.

Abstract: A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented (290) that uses un-rolled pipelined CORDIC processors (245a to 245d) iteratively to improve throughput and resource utilization, while reducing the gate count.

Abstract: A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.

Abstract: Methods and systems for maximum achievable efficiency in near-field coupled wireless power transfer systems may comprise, for example, configuring coil geometry for a transmit (Tx) coil and a receive (Rx) coil based on a media expected to be between the coils during operation. A desired susceptance and conductance may be determined and an impedance of an amplifier for the Tx coil may be configured based on the determined susceptance and conductance. A load impedance for the Rx coil may be configured based on the determined susceptance and conductance. A matching network may be coupled to the amplifier. The Rx coil may be integrated on a complementary metal-oxide semiconductor (CMOS) chip. One or more matching networks may be integrated on the CMOS chip for the configuring of the load impedance for the Rx coil.

Abstract: Methods and systems for a complementary metal oxide semiconductor wireless power receiver may include a receiver chip with an inductor, a configurable capacitance, and a rectifier. The method may include receiving an RF signal utilizing the inductor, extracting a clock signal from the received RF signal, generating a DC voltage utilizing a rectifier circuit, sampling the DC voltage, and adjusting the configurable capacitance based on the sampled DC voltage. The rectifier circuit may include CMOS transistors and T-gate switches for coupling to the inductor. The T-gate switches may be controlled by the generated DC voltage. A signed based gradient-descent algorithm may be utilized to maximize the DC voltage. The DC voltage may be sampled utilizing a comparator powered by the DC voltage, which may adaptively configure the capacitance. The inductor may be shielded utilizing a floating shield. The DC voltage may be increased utilizing a voltage-boosting rectifier.

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract: An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2NT?1 (NT=number of transmit antennas) on-demand to only 2K?1 lowest Partial Euclidean Distance (PED) paths at last tree level 2NT. The relaxed LLR computation scheme includes approximating LLR computations by assuming that discarded path PED is greater than or equal K-Best path PED.

Abstract: One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.

Abstract: Methods and systems for maximum efficiency achievable in near-field coupled wireless power transfer systems are disclosed and may include configuring coil geometry, independently of load impedance and source impedance, for a transmit (Tx) coil and a receive (Rx) coil based on a media expected to be between the coils during operation. A desired susceptance and conductance may be determined and an impedance of an amplifier for the Tx coil may be configured based on the determined susceptance and conductance. A load impedance for the Rx coil may be configured based on the determined susceptance and conductance. A matching network may be coupled to the amplifier. The Rx coil may be integrated on a complementary metal-oxide semiconductor (CMOS) chip. One or more matching networks may be integrated on the CMOS chip for the configuring of the load impedance for the Rx coil.

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract: Methods and systems for maximum efficiency achievable in near-field coupled wireless power transfer systems are disclosed and may include configuring coil geometry, independently of load impedance and source impedance, for a transmit (Tx) coil and a receive (Rx) coil based on a media expected to be between the coils during operation. A desired susceptance and conductance may be determined and an impedance of an amplifier for the Tx coil may be configured based on the determined susceptance and conductance. A load impedance for the Rx coil may be configured based on the determined susceptance and conductance. A matching network may be coupled to the amplifier. The Rx coil may be integrated on a complementary metal-oxide semiconductor (CMOS) chip. One or more matching networks may be integrated on the CMOS chip for the configuring of the load impedance for the Rx coil.

Abstract: A sensor for detecting an electric field fluctuation associated with the permeabilization of a bacterial cell wall comprises a substrate, at least two electrodes integrated on the substrate, an amplifier integrated on the substrate, and a processor electrically connected to the amplifier to analyze the amplified signal. The substrate and the at least two electrodes define a well between the at least two electrodes, and the at least two electrodes being configured to generate a signal in response to an electric field fluctuation in close proximity to the well or the electrodes triggered when at least one antibacterial agent associated with the well contacts a cognate target. The amplifier is configured to generate an amplified signal in response to the signal. In addition, the processor is electrically connected to the amplifier to analyze the amplified signal.

Abstract: Disclosed are methods and systems for the detection of bacteria in a sample. The methods comprises contacting the sample with an antibacterial agent and a bacteria identification sensor, and involves the permeabilization of the bacteria by the antibacterial agent, and the subsequent detection of an efflux of potassium ions using a bacteria identification sensor comprising a potassium-sensitive ISFET. Also disclosed are bacteria identification sensor comprising a potassium-sensitive ISFET useful in the practice of the disclosed methods.