Abstract: One or more circuits may include an array of memory cells corresponding to a particular memory address. The one or more circuits may be operable to discover a location of a faulty memory cell in the array of memory cells. The one or more circuits may be operable to arrange the order in which the bits of a data block are stored to said array of memory cells based, at least in part, on said discovered location of said faulty memory cell.

Abstract: An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2NT?1 (NT=number of transmit antennas) on-demand to only 2K?1 lowest Partial Euclidean Distance (PED) paths at last tree level 2NT. The relaxed LLR computation scheme includes approximating LLR computations by assuming that discarded path PED is greater than or equal K-Best path PED.

Abstract: One or more circuits may include an array of memory cells corresponding to a particular memory address. The one or more circuits may be operable to discover a location of a faulty memory cell in the array of memory cells. The one or more circuits may be operable to arrange the order in which the bits of a data block are stored to said array of memory cells based, at least in part, on said discovered location of said faulty memory cell.

Abstract: One or more circuits may comprise an array of memory cells corresponding to a particular memory address, and a memory fault mitigation module. The one or more circuits may be operable to write a data block to the array of memory cells. The write operation may comprises a swap of a first portion of the data block with a second portion of the data block in response to a detection that one or more memory cells of the array is faulty, and storing the data block to the array of memory cells after the swap.

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract: A plurality of data lines and a plurality of bit lines may be used to write to and/or read from an array of memory cells. A switching element may select among different mappings between the plurality of data lines and the plurality of bit lines. The array may, for example, consist of N memory cells, the plurality of bit lines may consist of N bit lines, and the plurality of data lines may consist of N data lines, where N is an integer greater than 1. For a write operation in which a data block is to be written to the array, a configuration of the switching element may be controlled based, at least in part, on how sensitive the data block is to a faulty memory cell among the array of memory cells.

Abstract: An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2NT?1 (NT=number of transmit antennas) on-demand to only 2K?1 lowest Partial Euclidean Distance (PED) paths at last tree level 2NT. The relaxed LLR computation scheme includes approximating LLR computations by assuming that discarded path PED is greater than or equal K-Best path PED.

Abstract: A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented (290) that uses un-rolled pipelined CORDIC processors (245a to 245d) iteratively to improve throughput and resource utilization, while reducing the gate count.

Abstract: A sensor for detecting an electric field fluctuation associated with the permeabilization of a bacterial cell wall comprises a substrate, at least two electrodes integrated on the substrate, an amplifier integrated on the substrate, and a processor electrically connected to the amplifier to analyze the amplified signal. The substrate and the at least two electrodes define a well between the at least two electrodes, and the at least two electrodes being configured to generate a signal in response to an electric field fluctuation in close proximity to the well or the electrodes triggered when at least one antibacterial agent associated with the well contacts a cognate target. The amplifier is configured to generate an amplified signal in response to the signal. In addition, the processor is electrically connected to the amplifier to analyze the amplified signal.

Abstract: Binary and multiple-valued nonvolatile content addressable memories (NVCAMs) use ferroelectric capacitors as nonvolatile storage elements. The operation of the NVCAMs is accessed either in serial or in parallel. In a 2-bit NVCAM of a parallel access structure, search operation is performed by a simultaneous access to a 4-level polarization of the ferroelectric capacitor. The total number of search operations is reduced.

Abstract: Binary and multiple-valued nonvolatile content addressable memories (NVCAMs) use ferroelectric capacitors as nonvolatile storage elements. The operation of the NVCAMs is accessed either in serial or in parallel. In a 2-bit NVCAM of a parallel access structure, search operation is performed by a simultaneous access a 4-level polarization of the ferroelectric capacitor. The total number of search operations is reduced.