Patents by Inventor Glenn Rinne

Glenn Rinne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5374893
    Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: December 20, 1994
    Assignee: MCNC
    Inventors: Nicholas G. Koopman, Glenn A. Rinne, Iwona Turlik, Edward K. Yung
  • Patent number: 5315485
    Abstract: Capture pads of variable size are provided on the face of a multilayer ceramic substrate, to accommodate the actual shrinkage tolerance of the substrate at each capture pad position. For example, assuming a minimum shrinkage reference point is at the center of the substrate face, the capture pad size is relatively large adjacent the edges of the substrate face and relatively small adjacent the center of the substrate face. By sizing each capture pad based on the maximum positional variation at the particular capture pad position, higher contact density is obtainable than with known uniform size capture pads. The variable size capture pads may also be used at one or more rows of capture pads located along one or more edges of the substrate, for electrical connection to an edge connector. For example, assuming a minimum shrinkage reference point at the center of the row, the capture pads are relatively large adjacent the ends of the row of capture pads and are relatively small adjacent the center of the row.
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: May 24, 1994
    Assignees: MCNC, Northern Telecom Limited
    Inventors: Paul A. Magill, Nicholas G. Koopman, Glenn A. Rinne
  • Patent number: 5289631
    Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.
    Type: Grant
    Filed: March 4, 1992
    Date of Patent: March 1, 1994
    Assignee: MCNC
    Inventors: Nicholas G. Koopman, Glenn A. Rinne, Iwona Turlik, Edward K. Yung