Abstract: In an organic electronic circuit (C), particularly a memory circuit with an organic ferroelectric or electret material (2) the active material comprises fluorine atoms and consists of various organic materials. The active material is located between a first electrode and a second electrode. A cell with a capacitor-like structure is defined in the active material and can be accessed for an addressing operation via a first and a second electrode. At least one of these electrodes (1a, 1b) comprises a layer of chemically modified gold. In a passive matrix-addressable electronic device, particularly a ferroelectric or electret memory device, circuits (C) of this kind with the active material as a ferroelectric or electret memory material form the elements of a matrix-addressable array and define the memory cells provided between first and second set of addressing electrodes. At least the electrodes of at least one of the sets then comprise at least a layer of gold.

Abstract: An electrical via connection and associated contact means in an organic electronic circuit, particularly a memory circuit is provided interfacing a layer of active organic dielectric material comprising various organic compounds. The via connection is provided in a via opening extending through the active dielectric material and connected with first and second electrical contact means on either side thereof. The second contact means comprises a first layer of chemically inert and non-reactive conducting material deposited directly on active dielectric layer, and a conducting material provided as a second layer over the first layer and in via opening down to the first contact means, creating a via connection through the active dielectric layer and connecting the first and the second contact means.—In a method for manufacturing an electric via connection and associated contact means of this kind, a first layer in a second contact means is deposited on the active dielectric layer.

Abstract: In a method for enhancing the data storage capability of ferroelectric or electret memory cell which has been applied to storage of data and attained an imprint condition, suitable voltage pulses are used for evoking a temporary relaxation of the imprint condition into a volatile polarization state that can be discriminated from the imprinted polarization state in a non-destructive readout operation. Sequences of one or more voltage pulses are used to evoke readout signals respectively indicative of a non-volatile and a volatile polarization state of the memory cell, but without altering said polarization states.

Abstract: In a method for forming interlayer connections, metal conducting paths in an overlaying layer and vias forming the deposit in one and the same operation. In an interlayer connection formed in this manner the vias are provided integral with connecting conducting paths in the overlaying layer.

Abstract: An organic electronic device consists of one or more electro-active organic or polymer materials sandwiched between electrodes. Critical in such devices is the interface between the electrode and the polymer, where degradation or chemical reaction products may develop that are deleterious to the proper functioning of the device. This is solved by introducing a functional interlayer composed of one or more materials consisting of a molecular backbone bearing phosphonate or phosphate functions, either directly attached or through side chains, said functional layer being disposed between at least one of the respective electrodes and said one or more electro-active materials in the device.

Abstract: A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

Abstract: A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

Abstract: In a method in the fabrication of an organic thin-film semiconducting device comprising an electrode arrangement with electrodes contacting a semiconducting organic material, an anode in the electrode arrangement is made as a two-layer structure, where the first layer is a conducting or semiconducting material or a combination thereof deposited on a substrate and a second layer is a conducting polymer with a work function higher than that of the material in the first layer. A third layer consisting of semiconducting organic material and forming the active material of the device is deposited on the top of the anode, and the cathode made of a fourth layer of a metal deposited on a third layer. In a preferred embodiment a low work function metal is used in the first layer, a doped conjugated polymer such as PEDOT-PSS in the second layer, while the cathode may be formed of the same metal as used in the first layer.

Abstract: A ferroelectric memory device wherein the memory cell includes a first and second electrode having at least one metal layer and possibly at least one metal oxide layer. The first electrode is formed on a silicon substrate which has an optional insulating layer of silicon dioxide. A ferroelectric layer consisting of a thin film of ferroelectric polymer if formed on the top of the first electrode layer and at least a second electrode is formed on the ferroelectric layer. The ferroelectric memory includes at least a first and a second set of respectively parallel electrodes, wherein the electrodes in a set are provided orthogonally to the electrodes of a nearest following set and with memory cells formed in a ferroelectric layer provided between successive electrode sets, such that the memory cells are defined in the crossings between the electrodes which contact the ferroelectric layer on each side thereof.

Abstract: In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto.

Abstract: A data storage/processing apparatus includes ROM and/or WORM and/or REWRITEABLE memory modules and/or processing modules provided as a single main layer or multiple main layers on top of a substrate. Transistors and/or diodes operate the apparatus. In one set of embodiments, at least some of the transistors and/or diodes are provided on or in the substrate. In another set of embodiments, at least some of the layers on the top of the substrate include low-temperature compatible organic materials and/or low temperature compatible processes inorganic films, and the transistors and/or diodes need not be disposed on or in the substrate. In a related fabricating method, the memory and/or processing modules are provided on the substrate by depositing the layers in successive steps under thermal conditions that avoid subjecting an already-deposited, processed underlying layers to static or dynamic temperatures exceeding given stability limits, particularly with regard to organic materials.

Abstract: In a method for forming interlayer connections, metal conducting paths in an overlying layer and vias forming the connections to conducting paths on an underlying layer are both deposited in one and the same operation. In an interlayer connection formed in this manner the vias are provided integral with connecting conducting paths in the overlying layer.

Abstract: A floor heating bendable, electrically conductive, thermoplastic mat having at least two electrodes arranged along each side edge of the mat. The mat includes a material composition whose volume resistivity increases substantially with an increase of temperature of the material composition below 30° C. The material composition comprises a semicrystalline polymer and an electrically conductive filler material. The polymer has a crystalline melting point which exceeds a normal working temperature of the mat but is below 99° C. and whose softening temperature (Vicat) is in a range of 45-70° C. The mat is self regulating regarding temperature and power for floor heating.

Abstract: In a memory and/or data processing device having at least two stacked layers (L) which are supported by a substrate (2) or forming a sandwiched self-supporting structure, wherein the layers (L) comprise memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate (2), the layers (L) are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor (3) is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack.

Abstract: In a non-volatile passive matrix memory device (10) comprising an electrically polarizable dielectric memory material (12) exhibiting hysteresis, first and second sets (14; 15) of addressing electrodes constitute word lines (WL) and bit lines (BL) of the memory device. A memory cell (13) is defined in the memory material (12) at the overlap between a word line (WL) and a bit line (BL). The word lines (WL) are divided into segments (S) with each segments sharing and being defined by adjoining bit lines (BL). Means (25) are provided for connecting each bit line (BL) of a segment (S) with a sensing means (26), thus enabling simultaneous connections of all memory cells (13) of a word line segment (15) for readout via the bit lines (BL) of the segment (S). Each sensing means (26) senses the charge flow in a bit line (BL) in order to determine a stored logical value.

Abstract: In a scalable data processing apparatus, particularly a data storage apparatus, one or more thin-film devices which form a substantially planar layer comprise a plurality of sublayers of thin film. Two or more thin-film devices are provided as an integrated stack of the substantially planar layers which form the thin-film devices, such that the apparatus thereby forms a stacked configuration. Each thin-film device comprises one or more memory areas which form matrix addressable memories and additionally circuit areas which form electronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said interfaces being realized with communication and signal lines as well as supporting circuitry for processing extending vertically through dedicated interface areas in the thin-film device.

Abstract: A device for floor heating comprising a bendable, electrically conductive, thermoplastic mat (1), adapted for division into lengths and mounting of these lengths side by side underneath a floor. The device is provided with at least two electrodes (4) arranged along each side edge (3) of the mat (1) each, to which electrodes (4) a current is connectable. The current is conducted through the device, which heats up and emits heat. The mat (1) comprises a material composition whose volume resistivity increases with the increase of the temperature of the material composition. The electrodes (4) are threadlike and the material composition comprises a semicrystalline polymer, whose crystalline melting point exceeds the normal working temperature of the device but are below 99° C. and whose softening temperature (Vicat) is in the range of 45-70° C., and an electrically conductive filler material.

Abstract: A field-effect transistor is made with electrodes (2, 4, 5) and isolators (3) in vertically provided layers, such that at least the electrodes (4, 5) and the isolators (3) form a step (6) oriented vertically relative to the first electrode (2) or the substrate (1). Implemented as a junction field-effect transistor (JFET) or a metal-oxide semiconducting field-effect transistor (MOSFET) the electrodes (2, 5) forming respectively the drain and source electrode of the field-effect transistor or vice versa and the electrode (4) the gate electrode of the field-effect transistor. Over the layers in the vertical step (6) an amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material is provided and forms the active semiconductor of the transistor contacting the gate electrode (8) directly or indirectly and forming a vertically oriented transistor channel (9) of the p or n type between the first (2) and the second (5) electrode.

Abstract: In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto.

Abstract: In a non-volatile passive matrix memory device comprising an electrically polarizable dielectric memory material exhibiting hysteresis between first and second sets of addressing electrodes, the electrodes of the first set are word lines and the electrodes of the second set are bit lines of the memory device. A memory cell with a capacitor-like structure is defined in the memory material at the overlap between a word line and a bit line. The word lines are divided into segments with each segments sharing and being defined by adjoining bit lines and means are provided for connecting each bit line of a segment with a sensing means, thus enabling simultaneous connections of all memory cells of a word line segment for readout via the bit lines of the segment. Each sensing means senses the charge flow in a bit line in order to determine a logical value stored in a memory cell defined by the bit line.