Patents by Inventor Graham Andrews

Graham Andrews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090094687
    Abstract: This document discusses, among other things, a system and method for detecting an initiation of a transaction and generating a string of characters based on the detection. A first portion of the string of characters may be presented in such a way as to be distinguished from a second portion of the string of characters. In various example embodiments, the transaction is validated based on an identification of the first portion of the string of characters.
    Type: Application
    Filed: October 3, 2007
    Publication date: April 9, 2009
    Applicant: eBay Inc.
    Inventors: Grahame Andrew Jastrebski, Dhanurjay A.S. Patil
  • Publication number: 20090002357
    Abstract: In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.
    Type: Application
    Filed: January 29, 2007
    Publication date: January 1, 2009
    Inventors: Gareth John, Patrick Zebedee, Michael James Brownlow, Tim Gasser, Jeremy Lock, Graham Andrew Cairns, Jaganath Rajendra, Harry Garth Walton
  • Publication number: 20080269848
    Abstract: The invention provides a hand held hair treatment device for the stimulation of hair growth on the scalp, which device comprises: a housing which includes a handle portion and a head portion; a plurality of hollow tines, each tine having a proximal end affixed to the head portion, a longitudinal length extending from the head portion and a distal end terminating in a tip section; a light source disposed within the housing and configured to output light; light guide means for channeling the light from the light source through the tines, and optical devices which are located at the distal ends of the tines; characterised in that the optical devices are configured to spread light which is incident upon them in an outward direction from the distal ends of the tines and onto the surface of the scalp to be treated.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 30, 2008
    Inventors: John Joseph Birmingham, Jason Shaun Burry, Ian Hopkinson, Graham Andrew Turner
  • Publication number: 20080261918
    Abstract: A compound of any of formulas (I) to (V): wherein at least one of Y and Z includes a Si atom, is of utility in therapy.
    Type: Application
    Filed: December 16, 2003
    Publication date: October 23, 2008
    Inventors: Graham Andrew Showell, Louise Marie Walsh, Ajay Kumar Mandal, David John Miller
  • Patent number: 7407649
    Abstract: A compound of formula (I) or formula (II) wherein the variables are as defined in the claims
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: August 5, 2008
    Assignee: Paradigm Therapeutics Ltd
    Inventors: David John Miller, Parminder Kaur Ruprah, Graham Andrew Showell, Louise Marie Walsh
  • Publication number: 20080150924
    Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
    Type: Application
    Filed: February 21, 2008
    Publication date: June 26, 2008
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hidehiko Yamashita, Hajime Washio, Yasushi Kubota, Graham Andrew Cairns, Michael James Brownlow
  • Patent number: 7365727
    Abstract: A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: April 29, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masakazu Satoh, Yasushi Kubota, Hajime Washio, Kazuhiro Maeda, Michael James Brownlow, Graham Andrew Cairns
  • Patent number: 7358950
    Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: April 15, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidehiko Yamashita, Hajime Washio, Yasushi Kubota, Graham Andrew Cairns, Michael James Brownlow
  • Patent number: 7339570
    Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: March 4, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Hajime Washio, Michael James Brownlow, Graham Andrew Cairns, Yasuyoshi Kaise, Kazuhiro Maeda
  • Patent number: 7329403
    Abstract: Cosmetic compositions in the form of soft solids having in combination an improved resistance to syneresis and retained efficacy and which contain a particulate antiperspirant suspended in a water-immiscible carrier liquid structured by a structurant system are obtainable by employing as carrier liquid a mixture of a hydrocarbon oil and an aromatic ester oil in a weight ratio of from 1:2 to 15:1 and as structurant system from 5.5 to 20% in total of a di or triblock alkylene/arylene block copolymer and an organic wax in a weight ratio to each other of from 5:1 to 30:1.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: February 12, 2008
    Assignee: Unilever Home & Personal Care USA Division of Conopco, Inc.
    Inventors: Beng Sim Chuah, Bruce Steven Emslie, Kevin Ronald Franklin, Daniel Albert Martindale, Graham Andrew Turner
  • Patent number: 7212184
    Abstract: In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: May 1, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hajime Washio, Yasushi Kubota, Kazuhiro Maeda, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
  • Patent number: 7190338
    Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: March 13, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Hajime Washio, Michael James Brownlow, Graham Andrew Cairns, Yasuyoshi Kaise, Kazuhiro Maeda
  • Patent number: 7093121
    Abstract: A request for secure data sent from a client computer 2 to a webtsite server computer 4 is redirected to a proxy computer 6. A secure connection is established with the proxy computer 6 using a protocol such as HTTP and Certificate Exchange. The proxy computer 6 then establishes its own secure connection with the website server 4. The data requested is passed in encrypted form from the website server computer 4 to the proxy computer 6. The proxy computer 6 decrypts this data and then scans it for illegal content, such as computer viruses, worms, Trojans, banned computer files, banned words, banned combinations of words or banned images and the like. Providing no illegal content is found, the data is encrypted again for transfer over the secure link between the proxy computer 6 and the client computer 2. The proxy computer 6 may conveniently be the firewall computer within a local area network.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: August 15, 2006
    Assignee: McAfee, Inc.
    Inventors: Christopher Andrew Barton, Graham Andrew Clarke, Simon Crowe
  • Patent number: 7042433
    Abstract: A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: May 9, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasushi Kubota, Hajime Washio, Kazuhiro Maeda, Graham Andrew Cairns, Michael James Brownlow
  • Patent number: 7028040
    Abstract: A method and system are provided for incrementally maintaining digital information using change notifications. A content store provides change notifications corresponding to changes to the data within the store to an event broadcaster. One or more modules store a subset of the content data for publication and receive the change notifications over a message queue bus. The modules process the change notifications and generate events for redistribution by the event broadcaster. The events may include publishing updated content by the modules.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: April 11, 2006
    Assignee: Microsoft Corporation
    Inventors: Stephen John Butler, Graham Andrew Ruffell
  • Patent number: 6970163
    Abstract: A frame rate controller (20) is provided for controlling the frame refresh rate of an active matrix display. The controller (20) comprises a first circuit such as a preloadable synchronous counter (21) which counts vertical synchronization signals VSYNC and supplies an enable signal FE for every Nth frame of data, where N is an integer greater than zero and is selectable. A gating arrangement (26) is controlled by the enable signal FE so that an active matrix display is refreshed for every Nth frame of data, thus allowing a reduction in power consumption of the display.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: November 29, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Graham Andrew Cairns, Michael James Brownlow
  • Patent number: 6952244
    Abstract: An active matrix devise comprises an array of picture elements. Each picture element has an image element, such as an LCD cell (11) connected to a first storage capacitor 12 and arranged to be connected to a data line 4 by an thin film transistor 10 when activated by a scan signal on a scan line 6. A second storage capacitor 21 can be connected across the first capacitor 12 by means of another thin film transistor 20 when desired so as to increase the storage capacitance at the pixel.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: October 4, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Graham Andrew Cairns, Catherine Rosinda Marie Armida Dachs, Michael James Brownlow, Yasuyoshi Kaise
  • Patent number: 6909417
    Abstract: A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: June 21, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hajime Washio, Yasushi Kubota, Kazuhiro Maeda, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
  • Patent number: 6852744
    Abstract: Novel pyrrolidine derivatives, being useful as chymase inhibitor or intermediate for synthesis of the active compounds, which has the formula (I): wherein R1 is cycloalkyl, substituted or unsubstituted phenyl or naphthyl, indanyl, thienyl, furyl, substituted or unsubstituted indolyl, benzofuryl, substituted or unsubstituted benzothienyl, etc.; R2 is H, alkyl, phenyl-lower alkyl, cycloalkyl or cycloalkyl-lower alkyl; R3 is (i) substituted or unsubstituted monocyclic heterocyclic group, (ii) substituted or unsubstituted benzene- or pyridine-fused heterocyclic group, or (iii) a group (a): R4 and R5 are independently H or OH, but R4 and R5 are not simultaneously H, or both form oxo; n is 0, 1, 2 or 3; or a salt thereof.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: February 8, 2005
    Assignee: Dainippon Pharmaceutical Co., Ltd.
    Inventors: Takashi Deguchi, Ryotaro Shiratake, Fuminori Sato, Buichi Fujitani, Yayoi Honda, Akihiko Kiyoshi, Mitsue Notake, Graham Andrew Showell, Robert George Boyle, Sukhbinder Singh Klair
  • Patent number: D575154
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: August 19, 2008
    Assignee: PepsiCo, Inc.
    Inventors: Graham Andrews, Patrick Finlay, Robert Le Bras-Brown, Laurent Hainaut