Abstract: A retention clip is configured to securely connect a first component to a second component. The retention clip includes a first frame connected to an opposed second frame by a central beam. An interior of the clip is defined between the first and second frames. Each of the first and second frames includes lateral legs that fold inwardly at upper bends, thereby forming flanges that are disposed within the interior. The flanges on respective sides of the clip are integrally connected by a bridging member, and the flanges further include distal ends that extend below a bottom edge of the bridging member. The clip further includes a flexible wing for securing the clip within the interior of a panel opening. Some embodiments of a retention clip include protrusions that extend inwardly from the bridging members.

Abstract: Systems and methods disclosed herein provide a method that includes obtaining, at a user device from a remote storage server, content relating to an electronic document, and rendering the content of the electronic document onto a first virtual rendering surface. The method further includes maintaining a second virtual rendering surface that stores a current state of the first virtual rendering surface. The method further includes obtaining an operation command relating to the electronic document, and retrieving first state information of the first virtual rendering surface and second state information of the second virtual rendering surface. The method further includes applying the operation command to the rendered content of the electronic document on the first virtual rendering surface, and updating at least one of the first state information or the second state information based on a type of the operation command.

Abstract: A first example box nut retainer includes a support, a fastener sleeve, a first wing, and a second wing. The support has a base and a tab extending from the base. The fastener sleeve defines an opening and extends downwardly from the base. The first wing extends from the base and has a snap arm. The second wing extends from the base and overlaps the first wing.

Abstract: A first example box nut retainer includes a support, a fastener sleeve, and a wing. The fastener sleeve defines an opening and extends downwardly from the support. The wing extends from the support and has a top corner between the support and the fastener sleeve.

Abstract: An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. The semiconductor device further includes a capacitor having a bottom plate above the substrate, a capacitor dielectric layer adjacent to and above the bottom plate, and a top plate adjacent to and above the capacitor dielectric layer. The bottom plate, the capacitor dielectric layer, and the top plate are within the first ILD layer or the second ILD layer. Furthermore, an air gap is formed next to the top plate and below a top surface of the second ILD layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Abstract: A device for reducing communications crosstalk including a plurality of channel inputs each configured to receive an incoming signal from a respective device. The device further includes at least one control input configured such that, when the control input is triggered, the control input activates a voltage divider that attenuates at least one of the incoming signals, thereby reducing crosstalk between a first channel carrying the at least one attenuated incoming signal and a second channel not carrying the at least one attenuated incoming signal. The at least one attenuated incoming signal and the remaining incoming signals are output to a respective receiver.

Abstract: Thin film transistors having alloying source or drain metals are described. In an example, an integrated circuit structure includes a semiconducting oxide material over a gate electrode. A pair of conductive contacts is on a first region of the semiconducting oxide material. A second region of the semiconducting oxide material is between the pair of conductive contacts. The pair of conductive contacts includes a metal species. The metal species is in the first region of the semiconducting oxide material but not in the second region of the semiconducting oxide material.

Abstract: An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.

Abstract: A baking device for a wafer coated with a coating containing a solvent is described, having a baking chamber, a support for the wafer, an inlet for a purge gas, and an evacuation for the purge gas charged with solvent evaporated from the coating. The inlet is formed as a diffusion element arranged above the wafer so as to admit the purge gas evenly over substantially the entire surface of the wafer, and the evacuation is formed as an evacuation ring which radially surrounds the diffusion element and is arranged at a ceiling of the baking chamber.

Abstract: A system for code development and execution includes a client interface and a client processor. The client interface is configured to receive user code for execution and receive an indication of a server that will perform the execution. The client processor is configured to parse the user code to identify one or more data items referred to during the execution. The client processor is also configured to provide the server with an inquiry for metadata regarding the one or more data items, receive the metadata regarding the one or more data items, determine a logical plan based at least in part on the metadata regarding the one or more data items; and provide the logical plan to the server for execution.

Abstract: A stud clip assembly is provided. The stud clip assembly includes a clip having a mounting platform and a retention platform. The mounting platform includes a mounting bore that extends away from the retention platform and that defines a mounting aperture. The mounting aperture includes a threaded portion formed therein and a collar arranged at a first end thereof. The stud clip assembly further includes a fastening element configured to be threaded into the threaded portion of the mounting aperture. The collar is configured to be crimped onto the fastening element.