Abstract: A driver/receiver circuit for use at one end of a simultaneous bi-directional differential signal line while being driven at the other end by a similar circuit. The driver/receiver circuit includes a differential driver, a differential receiver, an isolation circuit and an offset generator. The differential driver drives differential signal lines as a function of an output signal. The differential amplifier detects the differential voltage across the differential signal lines via the isolation circuit. The offset generator circuit receives the output signal and, in response, adds an offset to the input terminals of the differential amplifier. The offset cancels at least a portion of the differential voltage across the input terminals of the differential amplifier that results from the DOUT signal. The isolation circuit prevents the offset from significantly affecting the voltage across the differential signal lines.

Abstract: A driver/receiver circuit for use at one end of a simultaneous bi-directional differential signal line while being driven at the other end by a similar circuit. The driver/receiver circuit includes a differential driver, a differential receiver, an isolation circuit and an offset generator. The differential driver drives differential signal lines as a function of an output signal. The differential amplifier detects the differential voltage across the differential signal lines via the isolation circuit. The offset generator circuit receives the output signal and, in response, adds an offset to the input terminals of the differential amplifier. The offset cancels at least a portion of the differential voltage across the input terminals of the differential amplifier that results from the DOUT signal. The isolation circuit prevents the offset from significantly affecting the voltage across the differential signal lines.

Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is shifted to generate a slave impedance code. The slave impedance code is provided to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation.

Abstract: An input circuit that receives an input signal and generates an output signal as a function of the input signal includes a latching circuit and a time blanking circuit. The latching circuit detects a transition of the input signal and causes a corresponding transition of the output signal. The time blanking circuit prevents the output signal from transitioning again for a predetermined period. This period begins with essentially no delay from the transition of the output signal, which can reduce the input circuit's sensitivity to high frequency noise that may be present on transitions of the input signal.

Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is provided (as a slave impedance code) to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation. Using the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs.

Abstract: An input circuit that receives an input signal and generates an output signal as a function of the input signal includes a latching circuit and a time blanking circuit. The latching circuit detects a transition of the input signal and causes a corresponding transition of the output signal. The time blanking circuit prevents the output signal from transitioning again for a predetermined period. This period begins with essentially no delay from the transition of the output signal, which can reduce the input circuit's sensitivity to high frequency noise that may be present on transitions of the input signal.

Abstract: An input circuit includes a comparator circuit and a multi-reference circuit. The input circuit receives an input signal and generates an output signal as a function of the input signal and a reference signal received from the multi-reference circuit. The comparator circuit detects a crossing of the input signal relative to the reference signal and causes a corresponding transition of the output signal. In response to the transition of the output signal, the multi-reference circuit provides a different reference signal to the comparator circuit. The reference signals provided by the multi-reference circuit are selected to create hysteresis in the operation of the input circuit.

Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is provided (as a slave impedance code) to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation. Using the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs.

Abstract: A method of leakage test for an integrated circuit by sampling the RC time constant of leakage current of the pins of the integrated circuit.

Abstract: Multistage configuration and power setting for a processor includes an on-die configuration signal fuse block programmed during manufacturing, configuration signal Control and I/O circuitry, a configuration change control signal output indicating when the configuration signals are going to change, and voltage regulators and clock generators that rely on the configuration change control signal to begin the system configuration change and boot sequences. The processor actively drives its configuration signal states. Multistage configuration and power setting also enables the processor to change its configuration states during operation.

Abstract: A circuit that senses changes in the electrical characteristics of one or more solder joints, and generates one or more signals based, at least in part, on the electrical characteristics that are sensed, is incorporated into an integrated circuit. In a further aspect of the present invention, the one or more signals generated by the circuit are indicative of the reliability of the solder joints. Embodiments of the present invention provide a warning in advance of system failure, permitting repair or replacement of a failing unit/joint before a failure becomes catastrophic. Embodiments of the present invention include structures and circuitry that can determine whether solder joint failure has occurred, and that can communicate the occurrence of solder joint failure to other components or systems.

Abstract: A microprocessor motherboard and system include a microprocessor having external input and external output connections. The microprocessor includes a conductive path formed between one of the external input connections and an external output connection for routing a supply voltage to the external output connection. The microprocessor, therefore, selects an appropriate bus voltage for communicating with peripheral circuitry. New generations of microprocessors can be implemented without changing the remaining motherboard configuration.

Abstract: A dynamic processor configuration and power-up programs a processor's fuse block with configuration signals during processor manufacturing. The processor configuration signals include a core voltage identifier and a system bus frequency identifier. When power is applied to the platform, a control signal is used to prevent power-up of the platform's processor related circuitry. While the platform awaits full power-up, the fuse block is powered up. When the fuse block is powered up, the control signal is used to allow the configuration signals to be read from the fuse block. The processor is configured with core voltage and system bus frequency based on the values read from the fuse block. The platform then performs its boot-up sequence.

Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.

Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.

Abstract: A clocked sense amplifier flip flop includes at least one keeper unit to prevent the occurrence of a floating data node.

Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.

Abstract: An output buffer circuit includes an adjustable delay time and is coupled to a reference output buffer which includes an adjustable delay time and a fixed delay time. In one embodiment, a synchronous delay line circuit provides a reference signal having a predetermined delay time. The time delay is equal to 1/N of a clock signal cycle. The reference output buffer uses the reference signal to set a cumulative delay time for the reference output buffer equal to 1/N. The adjustable delay time of the output buffer is set equal to the adjustable time delay of the reference output buffer.

Abstract: An apparatus and method for detecting and measuring internal clock jitter is disclosed. In one embodiment, a reference clock generator generates a reference clock signal based on an instantaneous clock signal. The reference clock signal includes the instantaneous clock signal delayed for an average duration. A phase comparing element receives both the instantaneous clock signal and the reference clock signal such that the phase comparing element measures a phase difference between the instantaneous clock signal and the reference clock signal. The magnitude and direction of the phase difference is indicated by one of a number of distinct phase difference bins in the phase comparing element.

Abstract: Integrated circuits include an impedance control circuit having at least one output terminal coupled to an on-chip reference termination device in order to control output impedance of the reference termination device such that it matches that of an external resistance. The impedance control circuit outputs are also coupled to the on-chip impedance-controlled termination devices which are coupled to each of the external transmission lines to be terminated. In this way, a single reference resistance allows many transmission lines to be properly terminated. The impedance-controlled termination devices are may be implemented as pairs of binary weighted p-channel and n-channel field effect transistors.