Abstract: A method and an apparatus for biasing a charge pump in a phase locked loop in a circuit and generally for biasing a circuit through the use of a replica circuit. The method and apparatus make use of a replica circuit including substantially similar circuit elements to those circuit elements making up the circuit to be biased. Through the use of comparison and bias techniques, the replica circuit and the circuit to be biased are both biased. The bias conditions result from a comparison of the operation of the replica circuit and the circuit to be biased. Since the replica circuit operates in a manner substantially similar to an expected operation mode of the circuit to be biased, the bias conditions resulting from the comparisons will cause the circuit to be biased to operate similarly to how the replica circuit operates, while still handling external influences such as loading.

Abstract: Circuitry added to chips that use source synchronous techniques reduces difficulties associated with testing the chips. The circuitry increases the ability to use source synchronous techniques for data transmission. The circuitry is implemented in a delayed-lock loop (DLL) in either a transmitter (driver) or a receiver. The DLL measures the phase difference between a strobe signal and a delayed strobe signal. The DLL can be externally controlled by a source selectable input which allows the delay of the delayed strobe signal to be varied to test T.sub.setup and T.sub.hold in the receiver without varying the timings of the strobe signal and the data signals supplied to the chips. A timing measurement circuit having the strobe signal, the delayed strobe signal, and reference signals as inputs may be used to calibrate the phase difference between the strobe signal and delayed strobe signal.

Abstract: An apparatus that efficiently delivers electrical power and lowers the inductance to an integrated circuit. In one embodiment, the present invention includes an apparatus for delivering electrical power to an integrated circuit comprising two planes, substantially parallel to one another, having many ground and power traces. The ground and power traces of the separate planes are connected together and connected to the integrated circuit, thereby providing power to the integrated circuit. In each individual plane, the ground and power traces are substantially parallel to each other, one array of traces in one plane substantially perpendicular to another array of traces in another plane. The apparatus being electrically coupled to a printed circuit board having at least one decoupling capacitor with first and second electrodes coupled to at least two of the ground and power connections, respectively, of the integrated circuit through the printed circuit board, and the first and second ground and power planes.

Abstract: A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.

Abstract: A method and an apparatus for generating an output voltage for an integrated circuit having multiple power supplies. A comparator circuit is coupled to receive power supply lines from the power bus of an integrated circuit. The power supply lines received from the power bus have different voltages which may vary depending on the particular application. The comparator compares the voltage potentials present on the power supply lines and determines which power supply line carries a voltage having the highest potential. The comparator then generates a corresponding select signal wherein the value of the select signal indicates which particular power supply line has the highest voltage potential. A multiplexor is coupled to receive the select signal as well as the power supply lines from the power bus.

Abstract: A method and an apparatus for filtering noise from power supplied to a noise sensitive load. A voltage supply circuit is coupled between a first voltage and a second voltage provided on a chip. The voltage supply circuit is configured to supply third voltage. A filter circuit is coupled to the voltage supply circuit to receive and to filter the third voltage. A transistor is coupled between the first voltage and the noise sensitive load and the filter circuit is coupled between the gate of the transistor and the voltage supply circuit. The transistor is coupled in a source follower configuration so as to supply a filtered fourth voltage to the noise sensitive load. In one embodiment, the voltage supply circuit comprises a diode configured transistor such that the output third voltage is equal to the second voltage plus the threshold voltage of the source follower configure transistor.

Abstract: A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to receive an input clock signal to be filtered. The output of the latch is the filtered clock signal. The filtered clock signal has a logic state which corresponds to the logic state of the input clock signal when the trigger input has a first predetermined logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second predetermined logic state. A trigger circuit is provided which has an input coupled to the output of the latch and an output coupled to the trigger input of the latch. The trigger circuit outputs the second predetermined logic state to the trigger input of the latch for a time interval in response to a change in logic state of the filtered clock signal and outputs the first predetermined logic state after the time interval has expired.

Abstract: A highly reliable, large fan-in, high speed, BiCMOS circuit. The amount of MOS transistor parasitic capacitance appearing on the output line of the circuit is reduced by adding only emitter capacitance of bipolar transistors to the output line for each input to the basic logic circuit. Circuitry is provided to raise the base voltage of a reverse biased bipolar transistors to reduce or eliminate the reverse bias.

Abstract: A swing limiting circuit for limiting the voltage across the input of a BiCMOS sense amplifier includes first and second bipolar transistors each having their collectors coupled to a first supply potential and their emitters coupled to the respective bases of a pair of bipolar transistors forming the sense amplifier. First and second pass gate devices are utilized to couple the respected bases of the first and second transistors to the bit lines running through the memory so as to limit the voltage drop appearing across the bases of the first and second transistors. A pair of NMOS devices are configured as source followers in parallel with the bipolar transistors to keep the voltage at the bases of the differential pair from dropping below a predetermined level.

Abstract: A reference circuit for coupling to a particular type of BiCMOS logic gate includes a V.sub.be multiplier coupled between V.sub.CC and a first internal node. The multiplier establishes a predetermined potential at the internal node which determines the voltage swing across the PMOS load devices utilized in the BiCMOS logic gate. A first PMOS transistor, configured as a current source within the multiplier, has its source coupled to the internal node. A second PMOS transistor has its gate coupled to the gate and drain of the first PMOS transistor in a source-follower configuration so as to drive the source node of the second PMOS transistor to the predetermined potential. A reference PMOS transistor is coupled between V.sub.CC and the source node of the second PMOS transistor, with the gate of the reference PMOS transistor being commonly coupled to the gates of the PMOS load devices and to a reference potential.

Abstract: In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder (CSA) cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier and divider are pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include two-speed internal clocking for operation and testing, two-node clock stopping and distributed buffering of system clock signals.

Abstract: In a floating point ALU, a carry-lookahead adder circuit includes integral XOR logic means for complementing the sum bits responsive to an invert signal for generating the absolute value of the difference between two binary operands without added gate delay.

Abstract: In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recoded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier is pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include high-speed absolute value subtract circuitry for exponent calculations and normalizing floating point results.