Patents by Inventor Gregory G. Freeman
Gregory G. Freeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10191108Abstract: A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.Type: GrantFiled: November 19, 2015Date of Patent: January 29, 2019Assignee: Globalfoundries Inc.Inventors: Gregory G. Freeman, Siyuranga Koswatta, Paul S. McLaughlin, Daniel J. Poindexter, J. Campbell Scott, Scott Taylor, Gregory Uhlmann, James D. Warnock
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Patent number: 9953873Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: GrantFiled: May 24, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Patent number: 9906213Abstract: An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2nd stage first and second FET devices, each 2nd stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.Type: GrantFiled: November 6, 2015Date of Patent: February 27, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Gregory G. Freeman, Siyuranga O. Koswatta
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Publication number: 20170345719Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: ApplicationFiled: May 24, 2016Publication date: November 30, 2017Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Publication number: 20170146592Abstract: A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.Type: ApplicationFiled: November 19, 2015Publication date: May 25, 2017Inventors: Gregory G. Freeman, Siyuranga Koswatta, Paul S. McLaughlin, Daniel J. Poindexter, J. Campbell Scott, Scott Taylor, Gregory Uhlmann, James D. Warnock
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Publication number: 20170133923Abstract: An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2nd stage first and second FET devices, each 2nd stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.Type: ApplicationFiled: November 6, 2015Publication date: May 11, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Gregory G. Freeman, Siyuranga O. Koswatta
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Patent number: 9552455Abstract: An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.Type: GrantFiled: February 3, 2015Date of Patent: January 24, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel J. Poindexter, Gregory G. Freeman, Siyuranga O. Koswatta, J. Campbell Scott, Leon J. Sigal, James D. Warnock
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Publication number: 20160224717Abstract: An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.Type: ApplicationFiled: February 3, 2015Publication date: August 4, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Daniel J. Poindexter, Gregory G. Freeman, Siyuranga O. Koswatta, J. Campbell Scott, Leon J. Sigal, James D. Warnock
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Patent number: 9406569Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.Type: GrantFiled: October 21, 2014Date of Patent: August 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
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Patent number: 9305999Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.Type: GrantFiled: February 27, 2013Date of Patent: April 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao, Gregory G. Freeman
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Patent number: 9287399Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: October 7, 2014Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 9240354Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.Type: GrantFiled: November 14, 2012Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
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Publication number: 20150084096Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: October 7, 2014Publication date: March 26, 2015Inventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Publication number: 20150056760Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.Type: ApplicationFiled: October 21, 2014Publication date: February 26, 2015Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
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Patent number: 8940595Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: March 15, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Publication number: 20140264558Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Publication number: 20140131782Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.Type: ApplicationFiled: November 14, 2012Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
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Patent number: 8629501Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.Type: GrantFiled: February 10, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao, Gregory G. Freeman
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Patent number: 8232603Abstract: A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.Type: GrantFiled: February 9, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Gregory G. Freeman, Kevin McStay, Shreesh Narasimha
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Publication number: 20120139081Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.Type: ApplicationFiled: February 10, 2012Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huilong Zhu, Brian J. Greene, Dureseti Chidambarrao, Gregory G. Freeman