Abstract: A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area.

Abstract: A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation.

Abstract: Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion within the “ramp” of Ge concentration near the base-collector junction and a lower performance/lower variability type has an additional epi layer in the base so that the emitter diffusion intersects the Ge ramp where the ramp has a lower ramp rate.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: A non-uniform depth base-emitter junction, with deeper junction at the lateral portions of the emitter, preferably coupled with a recessed and raised extrinsic base, bipolar transistor, and a method of making the same. The bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a recessed and raised extrinsic base layer formed on the silicon germanium layer, and a silicon pedestal on which an emitter layer is formed. The emitter has non-uniform depths into the base layer.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing.

Abstract: A method for forming a heterojunction bipolar transistor includes forming two sets of spacers on the sides of an emitter pedestal. After the first set of spacers is formed, first extrinsic base regions are implanted on either side of an intrinsic base. The second set of spacers is formed on the first set of spacers. Second extrinsic base regions are then implanted on respective sides of the intrinsic base. By using two sets of spacers, the first and second extrinsic base regions have different widths. This advantageously brings the combined extrinsic base structure closer to the emitter of the transistor but not closer to the collector. As a result, the base parasitic resistance is reduced along with collector-to-extrinsic base parasitic capacitance. The performance of the transistor is further enhanced as a result of the extrinsic base regions being self-aligned to the emitter and collector.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.

Abstract: A method for forming a heterojunction bipolar transistor includes forming two sets of spacers on the sides of an emitter pedestal. After the first set of spacers is formed, first extrinsic base regions are implanted on either side of an intrinsic base. The second set of spacers is formed on the first set of spacers. Second extrinsic base regions are then implanted on respective sides of the intrinsic base. By using two sets of spacers, the first and second extrinsic base regions have different widths. This advantageously brings the combined extrinsic base structure closer to the emitter of the transistor but not closer to the collector. As a result, the base parasitic resistance is reduced along with collector-to-extrinsic base parasitic capacitance. The performance of the transistor is further enhanced as a result of the extrinsic base regions being self-aligned to the emitter and collector.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.

Abstract: High frequency performance of transistor designs is enhanced and manufacturing yield improved by removing and reducing sources of parasitic capacitance through combinations of processes from different technologies. After formation of collector, base and emitter regions on a substrate and attachment of a second substrate, the original substrate is wholly or partially removed, the inactive collector area is removed or rendered semi-insulating and wiring and contacts are made from the original back side of the chip. Dielectric material used in the manufacturing process can be removed to further reduce capacitance. The high frequency transistors can be bonded to CMOS chips or wafers to form BICMOS chips.

Abstract: Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.