Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract: The present invention provides a method of forming asymmetric field-effect-transistors.

Abstract: The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel positioned between the schottky barrier region and the drain dopant region. The semiconducting device may further include a gate structure overlying the channel of the semiconducting body. Further, a drain contact may be present to the drain dopant region of the semiconducting body, the drain contact being composed of a conductive material and in direct physical contact with a portion of a sidewall of the semiconducting body having a dimension that is less than a thickness of the semiconducting body in which the drain dopant region is positioned.

Abstract: The present invention provides a method of forming asymmetric field-effect-transistors.

Abstract: A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.

Abstract: Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

Abstract: An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.

Abstract: The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.

Abstract: Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

Abstract: A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.

Abstract: The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel positioned between the schottky barrier region and the drain dopant region. The semiconducting device may further include a gate structure overlying the channel of the semiconducting body. Further, a drain contact may be present to the drain dopant region of the semiconducting body, the drain contact being composed of a conductive material and in direct physical contact with a portion of a sidewall of the semiconducting body having a dimension that is less than a thickness of the semiconducting body in which the drain dopant region is positioned.

Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

Abstract: A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge.

Abstract: An integrated semiconductor device includes a resistor and an FET device formed from a stack of layers. The stack of layers includes a dielectric layer formed on a substrate; a metal conductor layer having lower electrical resistance formed on the dielectric layer; and a polysilicon layer formed on the metal conductor layer. A resistor stack is formed by patterning a portion of the original stack of layers into a resistor. An FET stack is formed from another portion of the original stack of layers. The FET stack is doped to form a gate electrode and the resistor stack is doped aside from the resistor portion thereof. Then terminals are formed at distal ends of the resistor in a doped portion of the polysilicon layer. Alternatively, the polysilicon layer is etched away from the resistor stack followed by forming terminals at distal ends of the metal conductor in the resistor stack.

Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract: The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.

Abstract: Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

Abstract: A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.

Abstract: The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

Abstract: A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.