Abstract: A tunable high impedance surface device (100) includes a conductive ground plane (105) and a plurality of conductive elements (110-114) electrically connected to the conductive ground plane (105). The device (100) also includes a plurality of capacitive elements (120-124) operable to vary a predetermined electromagnetic characteristic of the apparatus and standoffs (130, 132) between the plurality of capacitive elements (120-124) and the plurality of conductive elements (110-114). In one form, laser-drilled and electrically conductive micro-vias (136, 138) extend through the standoffs (130, 132) thereby electrically connecting the plurality of capacitive elements (120-124) to a data bus (140). The capacitive elements (120-124) may be integral with a circuit board (144) that supports the plurality conductive elements (110-114).

Abstract: Closed vias are formed in a multilayer printed circuit board by laminating a dielectric layer to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer.

Abstract: A method for forming closed vias in a multilayer printed circuit board. A dielectric layer is laminated to one side of a central core having a metal layer on each side. A second dielectric layer is laminated to the other side of the central core. Closed vias in the central core have been formed by drilling partially through but not completely penetrating the central core, and then completing the via from the opposite side with a hole that is much smaller in diameter to form a pathway that penetrates completely through the central core from one side to another. The via is then plated with metal to substantially close the smaller hole. Approximately one half of the closed vias are situated such that the closed aperture faces one dielectric layer and a remainder of the closed vias are situated such that the closed aperture faces the other dielectric layer.

Abstract: Fabricating (100, 1300) a printed circuit board includes fabricating patterned conductive traces (305, 310, 1410, 1415) onto a foil, laminating the patterned conductive traces to a printed circuit board substrate (405, 1505) by pressing on the foil, such that the conductive traces are pressed into a dielectric layer of the printed circuit board, and removing the foil to expose a co-planar surface of conductive trace surfaces and dielectric surfaces. Removal may be done by peeling (125) and/or etching (130, 1315).

Abstract: A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

Abstract: Embedded capacitors comprise a bimetal foil (500) that includes a first copper layer (205) and an aluminum layer (210) on the first copper layer. The aluminum layer has a smooth side adjacent the first copper layer and a high surface area textured side (215) opposite the first copper layer. The bimetal foil further includes an aluminum oxide layer (305) on the high surface area textured side of the aluminum layer, a conductive polymerlayer (420) on the aluminum oxide layer, and a second copper layer (535) overlying the aluminum oxide layer. The bimetal foil may be embedded in a circuit board (700) to form high value embedded capacitors.

Abstract: A textured dielectric patch antenna is fabricated by applying a first mask pattern (310, 510, 610, 710, 915, 1015, 1210) to a first side of a solid panel made of a first material that is a ceramic dielectric and then sandblasting the solid panel through the first mask pattern from the first side to at least partially generate a shaped cavity (315, 920, 1040). The shaped cavity of the solid panel may be filled with a second material (330, 740). The first and second materials have substantially differing dielectric constants. The first side and second side of the solid panel are metallized (325), forming a patch antenna. The shaped cavities can be made more complex by using additional masking and/or sandblasting steps.

Abstract: A sequentially laminated printed circuit board having highly reliable vias can be fabricated by pattern plating flanges or via lands on a copper foil, laminating the foil to a prepreg so that the flanges are embedded into the surface of the prepreg, creating via holes in the laminate that are substantially concentric with the individual flanges, plating the via holes with copper, chemically or mechanically milling off a portion of the copper plating and optionally some of the copper foil to reduce the overall thickness of the laminate, and laminating a second and optionally a third prepreg to the laminate. The resulting printed circuit board has the flanges embedded in the surface of the laminate so that the inside wall of the flange is electrically and mechanically attached to the outside wall of the plated through hole barrel.

Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic high temperature release structure (215) that comprises a co-deposited layer (250) and a metal oxide layer (260). The co-deposited layer comprises an admixture of nickel and one or more of boron, phosphorus, and chromium. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.

Abstract: A technique for fabricating a patterned resistor on a substrate produces a patterned resistor (101, 801, 1001, 1324, 1374) including two conductive end terminations (110, 810, 1010) on the substrate, a pattern of first resistive material (120, 815, 1015) having a first width (125) and a first sheet resistance, and a pattern of second resistive material (205, 820, 1020) having a second width (210) and a second sheet resistance that at least partially overlies the pattern of first resistive material. One of the first and second sheet resistances is a low sheet resistance and the other of the first and second resistances is a high sheet resistance. A ratio of the high sheet resistance to the low sheet resistance is at least ten to one. The pattern having the higher sheet resistance is substantially wider than the pattern having the low sheet resistance. The patterned resistor can be precision trimmed 1225.

Abstract: The invention provides an integrated device with corrosion-resistant capped copper bond pads. The capped copper bond pads include at least one copper bond pad on a semiconductor substrate. An activation layer comprising one of immersion palladium, electroless cobalt, or immersion ruthernium is disposed on the copper bond pad. A first intermediate layer of electroless nickel-boron alloy is disposed on the activation layer. A second intermediate layer comprising one of electroless nickel or electroless palladium is disposed on the first intermediate layer, and an immersion gold layer is disposed on the second intermediate layer. A capped copper bond pad and a method of forming the capped copper bond pads are also disclosed.

Abstract: A dielectric sheet (500, 600, 1621) includes a photodielectric support layer (505, 1630) that may be glass reinforced and a dielectric laminate (510, 605). The dielectric laminate includes first and second metal foil layers (415, 660; 210, 665, 1605, 1610), and a dielectric layer (405, 655, 1620) disposed between the first and second metal foil layers. The first metal foil layer is adhered to the photodielectric support layer. In a printed circuit and patch antenna that includes the dielectric sheet, the first metal layer is patterned by removal of metal according to a circuit pattern and the photodielectric support layer is patterned by removal of dielectric material according to the circuit pattern.

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

Abstract: A printed circuit polymer thick film (PTF) resistor includes tolerance control material that substantially surrounds the resistor body and significantly improves the linearity of resistance vs. resistor length, and significantly reduces resistor-to-resistor and board-to-board fabrication variances. In one embodiment, the tolerance control material is the same metallic material as the printed circuit conductors, and is formed in two finger patterns on each side of the resistor body, each finger pattern connected to one terminal pad of the resistor. A layout cell is used for fabricating the PTF resistor. A method is used for fabricating the PTF resistor.

Abstract: An integrated patch antenna and electronics assembly (300) comprises an antenna dielectric layer (305), a ground plane layer (310) disposed on a first side of the antenna dielectric layer, a printed circuit dielectric layer (315) disposed on the ground plane layer opposite the antenna dielectric layer, a patterned conductive metal foil layer (320) on a component surface (323) of the assembly (300), and a conductive metal foil antenna patch (325) disposed on a second side of the antenna dielectric layer that is in a patch side (391) of the assembly. In some embodiments, a plated through hole (330) couples the antenna patch to the patterned conductive metal foil layer. In some embodiments, there are one or more printed circuit dielectric layers (316, 341, 346, 351) disposed over the antenna patch on the antenna patch side of the assembly. In some embodiments, pairs of printed circuit dielectric layers ([315, 316], [340, 341], [345, 346], [350, 351]) are formed simultaneously on each side of the assembly.

Abstract: In one embodiment, a peelable circuit board foil (200) has a metal support layer (205) and a conductive metal foil layer (210) bonded by an inorganic release material (215). The conductive metal foil layer has a an exposed surface (212) that is coated with a high temperature anti-oxidant barrier (220) and has a roughness less than 0.05 microns RMS. In a second embodiment, the peelable printed circuit foil (200) has a crystallized dielectric oxide layer (405) disposed on the exposed surface of the conductive metal foil layer and an electrode layer (415) disposed on the crystallized dielectric oxide layer, forming a dielectric peelable circuit board foil (400) that may be adhered to a layer of a flexible or rigid circuit board, after which the metal support layer can be peeled away, leaving a capacitive structure including the metal foil layer, the crystallized dielectric oxide layer, and the electrode layer.

Abstract: A dielectric film is formed on a free-standing conductive metal layer to form a multi-layer foil comprising a conductive metal layer, a barrier layer and a dielectric oxide layer. Such multi-layer foils are mechanically flexible, and useful for the manufacture of capacitors. Examples of barrier layers include Ni—P or Ni—Cr alloys. After a second layer of conductive metal is deposited on a dielectric oxide surface opposing the first conductive metal layer, the resulting capacitor foil is processed into a capacitor. The resulting capacitor is a surface mounted capacitor or is formed as a integrated or embedded capacitor within a circuit board.

Abstract: A printed circuit polymer thick film (PTF) resistor includes tolerance control material that substantially surrounds the resistor body and significantly improves the linearity of resistance vs. resistor length, and significantly reduces resistor-to-resistor and board-to-board fabrication variances. In one embodiment, the tolerance control material is the same metallic material as the printed circuit conductors, and is formed in two finger patterns on each side of the resistor body, each finger pattern connected to one terminal pad of the resistor. A layout cell is used for fabricating the PTF resistor. A method is used for fabricating the PTF resistor.