Patents by Inventor Grigori Temkine
Grigori Temkine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130120930Abstract: A system and method for measuring integrated circuit (IC) temperature. An integrated circuit (IC) includes a thermal sensor and data processing circuitry. The thermal sensor utilizes switched currents provided to a reference diode and a thermal diode. The ratios of the currents provided to each of these diodes may be chosen to provide a given delta value between the resulting sampled diode voltages. At a later time, a different ratio of currents may be provided to each of these diodes to provide a second given delta value between the resulting sampled diode voltages. A differential amplifier within the data processing circuitry may receive the analog sampled voltages and determine the delta values. Other components within the data processing circuitry may at least digitize and store one or both of the delta values. A difference between the digitized delta values may calculated and used to determine an IC temperature digitized code.Type: ApplicationFiled: November 15, 2011Publication date: May 16, 2013Inventors: Grigori Temkine, Filipp Chekmazov, Paul Edelshteyn, Oleg Drapkin, Kristina Au
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Patent number: 8344760Abstract: A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an output buffer bias voltage based on the output voltage.Type: GrantFiled: July 17, 2009Date of Patent: January 1, 2013Assignee: ATI Technologies ULCInventors: Yamin Du, Oleg Drapkin, Grigori Temkine
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Patent number: 8290728Abstract: A method includes generating a first, second and third voltage output from a temperature sensing element of an integrated circuit using a respective, corresponding first, second and third, switched current source, for sequentially switching a respective first, second and third excitation current through the temperature sensing element. The third switched current source generates the corresponding third voltage output as a reference voltage between the first voltage and the second voltage. An error corrected difference is calculated between the first voltage and the second voltage using the reference voltage. In the method, the second excitation current is proportional to the first excitation current by a value n, and the third excitation current is proportional to the first excitation current by the square root of n.Type: GrantFiled: December 18, 2008Date of Patent: October 16, 2012Assignee: ATI Technologies ULCInventors: Oleg Drapkin, Grigori Temkine, Kristina Au, Filipp Chekmazov, Paul Edelshteyn
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Patent number: 8031538Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.Type: GrantFiled: June 26, 2009Date of Patent: October 4, 2011Assignee: ATI Technologies ULCInventors: Joseph Macri, Olge Drapkin, Grigori Temkine, Osamu Nagashima
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Patent number: 8031093Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.Type: GrantFiled: August 31, 2007Date of Patent: October 4, 2011Assignee: ATI Technologies ULCInventors: Kongning Li, Charles Leung, Grigori Temkine, Milivoje Aleksic, Steven Turner, Greg Vansickle, Kevin O'Neil
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Patent number: 8014125Abstract: Various capacitors for use with integrated circuits and other devices and fabrication methods are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first capacitor plate that has at least two non-linear strips and forming a second capacitor plate that has a non-linear strip positioned between the at least two non-linear strips of the first capacitor plate. A dielectric is provided between the non-linear strip of the second capacitor plate and the at least two non-linear strips of the first capacitor plate.Type: GrantFiled: November 26, 2007Date of Patent: September 6, 2011Assignee: ATI Technologies ULCInventors: Oleg Drapkin, Grigori Temkine, Kristina Au
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Patent number: 7932785Abstract: A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.Type: GrantFiled: August 23, 2004Date of Patent: April 26, 2011Assignee: ATI Technologies ULCInventors: Oleg Drapkin, Grigori Temkine, Mikhail Rodionov, Michael Foxcroft
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Publication number: 20100176848Abstract: A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an output buffer bias voltage based on the output voltage.Type: ApplicationFiled: July 17, 2009Publication date: July 15, 2010Applicant: ATI Technologies ULCInventors: Yamin Du, Oleg Drapkin, Grigori Temkine
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Publication number: 20100161261Abstract: A method includes generating a first, second and third voltage output from a temperature sensing element of an integrated circuit using a respective, corresponding first, second and third, switched current source, for sequentially switching a respective first, second and third excitation current through the temperature sensing element, wherein the third switched current source generates the corresponding third voltage output as a reference voltage between the first voltage and the second voltage; and calculating an error corrected difference between the first voltage and the second voltage using the reference voltage. In the method, the second excitation current is proportional to the first excitation current by a value n, and the third excitation current is proportional to the first excitation current by the square root of n.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Applicant: ATI TECHNOLOGIES ULCInventors: Oleg Drapkin, Grigori Temkine, Kristina Au, Filipp Chekmazov, Paul Edelshteyn
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Publication number: 20100149701Abstract: A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a shunt structure, such as a transistor, is interposed between a power node and a ground node. Circuitry is operative during a power up event or noise event, to render the shunt structure non-conductive for a period of time during the power up event or during the noise event (when power is applied). Second circuit is operative, during an electrostatic discharge event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a plurality of resistor/capacitors (RC) circuits are utilized wherein the RC circuits have different time constants.Type: ApplicationFiled: December 11, 2008Publication date: June 17, 2010Applicant: ATI Technologies ULCInventors: Oleg Drapkin, Grigori Temkine, Peter Bade
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Patent number: 7710150Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.Type: GrantFiled: March 12, 2008Date of Patent: May 4, 2010Assignee: ATI Technologies ULCInventors: Oleg Drapkin, Grigori Temkine, Arvind Bomdica, Kevin Liang
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Publication number: 20100013689Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.Type: ApplicationFiled: August 31, 2007Publication date: January 21, 2010Applicant: ATI Technologies ULCInventors: Kongning Li, Charles Leung, Grigori Temkine, Milivoje Aleksic, Steven Turner, Greg Vansickle, Kevin O'Neil
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Publication number: 20090323437Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.Type: ApplicationFiled: June 26, 2009Publication date: December 31, 2009Inventors: Joseph Macri, Olge Drapkin, Grigori Temkine, Osamu Nagashima
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Patent number: 7567467Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.Type: GrantFiled: October 15, 2004Date of Patent: July 28, 2009Assignee: ATI Technologies, ULCInventors: Joseph Macri, Olge Drapkin, Grigori Temkine, Osamu Nagashima
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Publication number: 20090133252Abstract: Various capacitors for use with integrated circuits and other devices and fabrication methods are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first capacitor plate that has at least two non-linear strips and forming a second capacitor plate that has a non-linear strip positioned between the at least two non-linear strips of the first capacitor plate. A dielectric is provided between the non-linear strip of the second capacitor plate and the at least two non-linear strips of the first capacitor plate.Type: ApplicationFiled: November 26, 2007Publication date: May 28, 2009Inventors: Oleg DRAPKIN, Grigori TEMKINE, Kristina AU
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Publication number: 20090086865Abstract: A differential signal comparator includes an input circuit operative to provide an absolute input current difference value that is associated with the absolute difference of differential input signal levels, and a reference circuit operative to provide an absolute reference current difference value that is associated with the absolute difference of the reference signal levels. Current comparison of the absolute input current difference value with the absolute reference current difference value identify whether an input differential signal is bigger than the reference noise level and should be processed, or an input differential signal is smaller than the reference noise level and should not be processed.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: ATI Technologies, Inc.Inventors: Oleg Drapkin, Grigori Temkine
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Publication number: 20080284468Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.Type: ApplicationFiled: May 15, 2007Publication date: November 20, 2008Inventors: Oleg Drapkin, Grigori Temkine, Marcus Ng, Kevin Yikai Liang, Arvind Bomdica, Siji Menokki Kandiyil, Ming So, Samu Suryanarayana
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Publication number: 20080157817Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.Type: ApplicationFiled: March 12, 2008Publication date: July 3, 2008Applicant: ATI Technologies ULCInventors: Oleg Drapkin, Grigori Temkine, Arvind Bomdica, Kevin Liang
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Patent number: 7385545Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.Type: GrantFiled: August 31, 2006Date of Patent: June 10, 2008Assignee: ATI Technologies Inc.Inventors: Kongning Li, Charles Leung, Grigori Temkine, Milivoje Aleksic, Steven Turner, Greg Vansickle, Kevin O'Neil
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Patent number: 7345510Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.Type: GrantFiled: August 31, 2006Date of Patent: March 18, 2008Assignee: ATI Technologies Inc.Inventors: Oleg Drapkin, Grigori Temkine, Arvind Bomdica, Kevin Liang