Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: A differential signal comparator includes an input circuit operative to provide an absolute input current difference value that is associated with the absolute difference of differential input signal levels, and a reference circuit operative to provide an absolute reference current difference value that is associated with the absolute difference of the reference signal levels. Current comparison of the absolute input current difference value with the absolute reference current difference value identify whether an input differential signal is bigger than the reference noise level and should be processed, or an input differential signal is smaller than the reference noise level and should not be processed.

Abstract: An integrated differential receiver includes a single gate oxide differential receiver and an associated switchable voltage supply circuit. The integrated differential receiver determines the desired receiver supply voltage and selects a supply voltage for the single gate oxide differential receiver. When a lower supply voltage is determined as the desired supply voltage, the integrated differential receiver automatically provides a supply voltage to the single gate oxide differential receiver with a voltage higher than the I/O pad supply voltage and higher than the maximum input signal voltage to increase the speed of operation for the differential receiver. The switchable voltage supply circuit is operatively responsive to a control signal which indicates the desired supply voltage for the I/O pad. In one embodiment, both the single gate oxide differential receiver and the switchable voltage supply circuit are single gate oxide circuits.

Abstract: A digitally programmable gain control circuit and method of operating the same is disclosed. The gain control circuit includes a programmable gain amplifier having an amplifier structure represented by a plurality of overlapping discrete monotonic transfer function segments, wherein at least one point of non-monotonicity occurs among one or more of the plurality of overlapping discrete monotonic transfer function segments, and a gain segment translator circuit operative to translate a monotonic gain value to a segment code to match the non-monotonic characteristics of the programmable gain amplifier. The programmability of the gain amplifier is provided by a coarse gain control circuit and a fine gain control circuit.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

Abstract: A differential signal comparator includes an input circuit operative to provide an absolute input current difference value that is associated with the absolute difference of differential input signal levels, and a reference circuit operative to provide an absolute reference current difference value that is associated with the absolute difference of the reference signal levels. Current comparison of the absolute input current difference value with the absolute reference current difference value identify whether an input differential signal is bigger than the reference noise level and should be processed, or an input differential signal is smaller than the reference noise level and should not be processed.

Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having single gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. The pre-buffer output signal has a level within normal gate voltage operating levels of the single gate oxide devices for each of the least a plurality of supply voltages. In one embodiment, the multi-supply voltage level shifting circuit includes a current mirror coupled to at least one of the first or second power supply voltage and also uses a non-linear device, such as a transistor configured as a diode, which is coupled to the output of current mirror. The non-linear device is coupled to receive a digital input signal from a signal source, such as from a section of core logic. A switching circuit coupled to the non-linear device selectively activates the non-linear device based on a level of the digital input signal.

Abstract: A method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of bit transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: A method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value or vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the method takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: An integrated circuit receiver includes a differential input receiver having a plurality of differential input transistors. A variable well voltage supply circuit varies the well voltages of the differential input transistors to change the input transistors threshold voltages to provide hysteresis control by varying well voltages of input transistors in opposite directions. A method for reducing noise for an integrated circuit receiver includes receiving an input signal by a differential input receiver, and changing into opposite directions the input transistors threshold voltages to provide hysteresis control by varying the first and second well voltages associated with each of a first differential input transistor and a second differential input transistor. At least one feedback signal is used from the differential input receiver as input to the variable well voltage supply circuit to vary the first and second well voltages to facilitate hysteresis control of the differential input receiver.

Abstract: A digitally programmable gain control circuit and method of operating the same is disclosed. The gain control circuit includes a programmable gain amplifier having an amplifier structure represented by a plurality of discrete monotonic transfer functions, wherein a point of non-monotonicity occurs between at least a plurality of the discrete monotonic transfer functions, and a gain segment translator circuit operative to translate a binary monotonic gain control code to a segmented binary code to match the non-monotonic characteristics of the programmable gain amplifier. The programmability of the gain amplifier is provided by a coarse gain control circuit and a fine gain control circuit.

Abstract: A spurious-free fractional-N frequency synthesizer circuit is disclosed. The synthesizer circuit includes a multi-phase network circuit operative to provide output signals that are at least a 1/(2n+1)) fractional version of the input signal. The synthesizer circuit includes a phase lock loop (PLL) circuit, with the multi-phase network circuit being coupled to the negative feedback loop of the PLL. The multi-phase network circuit includes a smoothing circuit that removes any jitter present at the output of the PLL.

Abstract: A spurious-free fractional-N frequency synthesizer circuit is disclosed. The synthesizer circuit includes a multi-phase network circuit operative to provide output signals that are at least a 1/(2n+1)) fractional version of the input signal. The synthesizer circuit includes a phase lock loop (PLL) circuit, with the multi-phase network circuit being coupled to the negative feedback loop of the PLL. The multi-phase network circuit includes a smoothing circuit that removes any jitter present at the output of the PLL.

Abstract: The present invention provides a memory device with a N-MOS self-termination scheme which enables or disables the device to eliminate ringing and line reflections in a memory device such as a DDR SDRAM. The self-termination is achieved by using a weak N-MOS transistor. The N-MOS transistors are within the device and has an impedance of two to eight times of the characteristic impedance of a communication path in a memory device such as DRAM or SRDAM. The communication path is generally a read/write or command/address bus. The self-termination scheme terminates line reflections occurring in a device receiving data during non productive time duration of system clock. The present invention provides a method by which random access memories perform with faster settling time for data inputs and a high system performance.

Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: A method and apparatus for simultaneously communicating data over a plurality of data links, such as a bus, determines initial logic levels of data to the output on each of the plurality of data links and changes the logic levels, such as inverting the data, of at least some of the data to produce logic level adjusted data in response to determining the initial logic level of the data to reduce switching transitions of simultaneously switched output data over the plurality of data links.