Patents by Inventor Griselda Bonilla
Griselda Bonilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140332965Abstract: An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect at the same level as the first including a second dual damascene via and wider line. The first and second interconnects may have different aspect ratio and may have different line heights while being co-planar with each other. The second line of the second interconnect may abut or partially surround the first line of the first interconnect. The first interconnect includes a refractory metal material as the main conductor, whereas the second interconnect includes a lower resistivity material as its main conductor.Type: ApplicationFiled: May 9, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20140319685Abstract: Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene.Type: ApplicationFiled: April 30, 2013Publication date: October 30, 2014Applicant: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20140302685Abstract: A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.Type: ApplicationFiled: June 18, 2014Publication date: October 9, 2014Inventors: Michael P. Belyansky, Griselda Bonilla, Xiao Hu Liu, Son V. Nguyen, Thomas M. Shaw, Hosadurga K. Shobha, Daewon Yang
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Publication number: 20140284815Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: ApplicationFiled: May 23, 2014Publication date: September 25, 2014Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, JR., Satyanarayana V. Nitta, Son Nguyen
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Patent number: 8836124Abstract: A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.Type: GrantFiled: March 8, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Samuel Sung Shik Choi, Ronald G. Filippi, Stephan Grunow, Naftali Eliahu Lustig, Andrew H. Simon
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Publication number: 20140256154Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, JR., Satyanarayana V. Nitta, Son Nguyen
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Publication number: 20140252538Abstract: A method of forming an electronic fuse including forming an Mx level including a first and a second Mx metal, forming a first Mx+1 dielectric above the Mx level, forming a conductive path on a portion of the first Mx+1 dielectric, forming a second Mx+1 dielectric above the first Mx+1 dielectric and above the conductive path, the first and second Mx+1 dielectrics together form an Mx+1 level, forming a first and a second via in the Mx+1 level, the conductive path extending from the first via to the second via and partially encircling the first via, and forming a first and second Mx+1 metal in the Mx+1 level, the first via extending vertically and electrically connecting the first Mx metal to the first Mx+1 metal, and the second via extending vertically and electrically connecting the second Mx metal to the second Mx+1 metal.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Naftali E. Lustig, Andrew H. Simon
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Patent number: 8809183Abstract: A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.Type: GrantFiled: September 21, 2010Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Lawrence A. Clevenger, Elbert E. Huang, Satyanarayana V. Nitta, Shom Ponoth
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Publication number: 20140217612Abstract: An electronic fuse structure including an Mx level comprising an Mx metal, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, where the Mx+1 metal comprises a thick portion and a thin portion, and where the Mx metal, the Mx+1 metal, and the via are substantially filled with a conductive material.Type: ApplicationFiled: February 6, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Erdem Kaltalioglu, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 8796133Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.Type: GrantFiled: July 20, 2012Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Timothy H. Daubenspeck, Mark C. H. Lamorey, Howard S. Landis, Xiao Hu Liu, David L. Questad, Thomas M. Shaw, David B. Stone
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Publication number: 20140203435Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.Type: ApplicationFiled: January 18, 2013Publication date: July 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
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Patent number: 8779600Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.Type: GrantFiled: January 5, 2012Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Son Van Nguyen, Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta
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Publication number: 20140183688Abstract: An electronic fuse structure including an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, and a nano-pillar located within the via and above the second Mx metal.Type: ApplicationFiled: January 2, 2013Publication date: July 3, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20140167268Abstract: A graphene and metal interconnect structure and methods of making the same are disclosed. The graphene is a multiple layer graphene structure that is grown using a graphene catalyst. The graphene forms an electrical connection between two or more VIAs or components, or a combination of VIAs and components. A VIA includes a fill metal, with at least a portion of the fill metal being surrounded by a barrier metal. A component may be a routing track, a clock signal source, a power source, an electromagnetic signal source, a ground terminal, a transistor, a macrocell, or a combination thereof. The graphene is grown, using a graphene catalyst, from both solid and liquid carbon sources using chemical vapor deposition (CVD) at a temperature between 300° C.-400° C. The graphene catalyst can be an elemental form of, or alloy including, nickel, palladium, ruthenium, iridium or copper.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20140167772Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: ApplicationFiled: February 25, 2014Publication date: June 19, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 8742766Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: GrantFiled: September 30, 2013Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 8736020Abstract: An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.Type: GrantFiled: September 10, 2012Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon
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Publication number: 20140127896Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.Type: ApplicationFiled: January 6, 2014Publication date: May 8, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Christos D. Dimitrakopoulos, Alfred Grill, James B. Hannon, Qinghuang Lin, Deborah A. Neumayer, Satoshi Oida, John A. Ott, Dirk Pfeiffer
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Publication number: 20140077334Abstract: An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via.Type: ApplicationFiled: September 20, 2012Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jinjing Bao, Griselda Bonilla, Samuel S. Choi, Daniel C. Edelstein, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon
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Publication number: 20140070363Abstract: An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.Type: ApplicationFiled: September 10, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon