Abstract: A method of forming an electronic fuse including forming an Mx level including a first and a second Mx metal, forming a first Mx+1 dielectric above the Mx level, forming a conductive path on a portion of the first Mx+1 dielectric, forming a second Mx+1 dielectric above the first Mx+1 dielectric and above the conductive path, the first and second Mx+1 dielectrics together form an Mx+1 level, forming a first and a second via in the Mx+1 level, the conductive path extending from the first via to the second via and partially encircling the first via, and forming a first and second Mx+1 metal in the Mx+1 level, the first via extending vertically and electrically connecting the first Mx metal to the first Mx+1 metal, and the second via extending vertically and electrically connecting the second Mx metal to the second Mx+1 metal.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract: E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.

Abstract: An electronic fuse structure including an Mx level comprising an Mx metal, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, where the Mx+1 metal comprises a thick portion and a thin portion, and where the Mx metal, the Mx+1 metal, and the via are substantially filled with a conductive material.

Abstract: A structure including a first metal line in a first interconnect level, the first metal line comprising one or more graphene portions, a second metal line in a second interconnect level above the first interconnect level, the second metal line comprising one or more graphene portions, and a metal via comprising a palladium liner extends vertically and electrically connects the first metal line with the second metal line, the via is at least partially embedded in the first metal line such that the palladium liner is in direct contact with at least an end portion of the one or more graphene portions of the first metal line.

Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.

Abstract: A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.

Abstract: In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material.

Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.

Abstract: An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via.

Abstract: An electronic fuse structure including an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, and a nano-pillar located within the via and above the second Mx metal.

Abstract: A method of forming an electronic fuse including providing an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, forming an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the second Mx metal to the Mx+1 metal in a vertical orientation, and forming a nano-pillar from the Mx cap dielectric at a bottom of the via and above the second Mx metal, the nano-pillar having a height less than a height of the via.

Abstract: An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via.

Abstract: An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Abstract: A structure including an Mx level including a first Mx metal, a second Mx metal, and a third Mx metal abutting and electrically connected in sequence with one another, the second Mx metal including graphene, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via, the via electrically connects the third Mx metal to the Mx+1 metal in a vertical orientation.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: A structure including a first interconnect including a first line overlying a first via and a second interconnect including a second line overlying a second via. The first line and the second line are co-planar. The first interconnect comprises a first conductor, the first conductor comprises a metal silicide including titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, molybdenum silicide, tantalum silicide, or some combination thereof. The second interconnect comprises a second conductor, the second conductor comprising copper.