Patents by Inventor Guan Chew
Guan Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8415236Abstract: A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.Type: GrantFiled: December 29, 2009Date of Patent: April 9, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Han Guan Chew, Jinping Liu, Alex Kai Hung See, Mei Sheng Zhou
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Publication number: 20130078809Abstract: A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.Type: ApplicationFiled: September 24, 2011Publication date: March 28, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Weibo Yu, Hsueh-Chin Lu, Han-Guan Chew, Kuo Bin Huang, Chao-Cheng Chen, Syun-Ming Jang
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Patent number: 8378428Abstract: The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ? of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ? of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.Type: GrantFiled: September 29, 2010Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Guan Chew, Lee-Wee Teo, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
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Publication number: 20130012011Abstract: This description relates to a method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS). The method includes forming a first opening in a dielectric layer over a substrate and partially filling the first opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the first opening. The method further includes forming a second opening adjoining the first opening in the dielectric layer over the substrate and depositing a first work-function metal layer in the first and second openings, whereby the first work-function metal layer is over the second work-function metal layer in the first opening. The method further includes depositing a signal metal layer over the first work-function metal layer in the first and second openings and planarizing the signal metal layer.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Guan CHEW, Ming ZHU, Lee-Wee TEO, Harry-Hak-Lay CHUANG
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Patent number: 8304842Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.Type: GrantFiled: July 14, 2010Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Guan Chew, Ming Zhu, Lee-Wee Teo, Harry-Hak-Lay Chuang
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Patent number: 8304831Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.Type: GrantFiled: February 8, 2010Date of Patent: November 6, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming Zhu, Lee-Wee Teo, Han-Guan Chew, Harry Hak-Lay Chuang
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Publication number: 20120208057Abstract: An electric energy store (10) of a motor vehicle, in particular a high voltage energy store of a hybrid vehicle or an electric vehicle, has a housing (11) and storage modules (12) accommodated in the housing. The housing (11) has a supporting element (17) with an annular supporting frame (18) made from a fiber reinforced plastic and via which the electric energy store (10) can be connected to a body structure of a motor vehicle.Type: ApplicationFiled: February 10, 2012Publication date: August 16, 2012Applicant: DR. ING. H.C.F. PORSCHE AKTIENGESELLSCHAFTInventors: Stefan Bender, Guan Chew, Steffen Maurer
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Publication number: 20120199406Abstract: A motor vehicle has an electrical drive machine that is supplied with electrical energy by an electrical energy storage device, and has an underbody region or surface (5). The electrical energy storage device is accessible for maintenance and/or installation work via a maintenance cover (10) in the underbody surface (5) to reduce time required for maintenance and/or installation work.Type: ApplicationFiled: February 3, 2012Publication date: August 9, 2012Applicant: DR. ING. H.C.F. PORSCHE AKTIENGESELLSCHAFTInventors: Stefan Bender, Guan Chew, Steffen Maurer
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Publication number: 20120083095Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.Type: ApplicationFiled: December 12, 2011Publication date: April 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Guan CHEW, Ming ZHU, Lee-Wee TEO, Harry-Hak-Lay CHUANG
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Publication number: 20120074475Abstract: The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ? of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ? of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.Type: ApplicationFiled: September 29, 2010Publication date: March 29, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Guan CHEW, Lee-Wee TEO, Ming ZHU, Bao-Ru YOUNG, Harry-Hak-Lay CHUANG
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Patent number: 8143137Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.Type: GrantFiled: February 17, 2010Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Guan Chew, Ming Zhu, Lee-Wee Teo, Harry-Hak-Lay Chuang
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Publication number: 20120012937Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.Type: ApplicationFiled: July 14, 2010Publication date: January 19, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Guan CHEW, Ming ZHU, Lee-Wee TEO, Harry-Hak-Lay CHUANG
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Publication number: 20110287295Abstract: A pouch-cell battery arrangement has a shrink sleeve covering (50), that surrounds the pouch (22) at least in places in an interlocking manner.Type: ApplicationFiled: May 9, 2011Publication date: November 24, 2011Applicant: DR. ING. H.C.F. PORSCHE AKTIENGESELLSCHAFTInventors: Dirk Lappe, Ralf Bauer, Hartmut Chodura, Guan Chew
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Publication number: 20110236741Abstract: An energy store for a motor vehicle for storage and emission of electrical energy as required, having a multiplicity of cells which are positioned one above the other and/or alongside one another like an array, wherein each cell is surrounded by a first material, wherein a second material is positioned between the cells which are surrounded by the first material and form a cell array, and wherein heat exchanging ribs are positioned at edges of the cell array.Type: ApplicationFiled: March 22, 2011Publication date: September 29, 2011Applicant: Dr. Ing. h.c. F. Porsche AktiengesellschaftInventors: Guan Chew, Miroslaw Oslislok, Hartmut Chodura, Stefan Bender
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Publication number: 20110230042Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.Type: ApplicationFiled: March 16, 2010Publication date: September 22, 2011Applicant: TAIWAN SEMICONDUCTOR MENUFACTURING COMPANY, LTD.Inventors: Han-Guan Chew, Ming Zhu, Lee-Wee Teo, Harry Hak-Lay Chuang, Yi-Ren Chen
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Publication number: 20110201172Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.Type: ApplicationFiled: February 17, 2010Publication date: August 18, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Guan CHEW, Ming Zhu, Lee-Wee Teo, Harry-Hak-Lay Chuang
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Publication number: 20110192659Abstract: A vehicle having an electric drive device and an energy storage device which is arranged in a housing is disclosed. The energy storage device is formed from a plurality of cells. The housing includes a plurality of partitioning devices, with the result that at least one partitioning device is positioned between two cells. The housing of the energy storage device is connected both to a cooling air intake duct, having an inlet opening, and to a cooling air outflow duct, having an outlet opening. At least one partitioning device is configured in such a way that a plurality of cooling ducts are formed between the cells, and cooling air can flow through the cooling ducts in order to cool the energy storage device.Type: ApplicationFiled: January 27, 2011Publication date: August 11, 2011Applicant: Dr. Ing. h.c. F. Porsche AktiengesellschaftInventors: GUAN CHEW, Miroslaw Oslislok, Hartmut Chodura, Patrik Gisch, Steffen Maurer, Ralf Bauer
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Publication number: 20110192660Abstract: A drive arrangement for an electric vehicle has an axle drive device of a portal design with two electric machines for driving the wheels of an axle of the electric vehicle, and at least one electric energy store that can be discharged when an electric machine is operated as a motor and/or can be charged when an electric machine is operated as a generator. The drive arranged is characterized in that the two electric machines (11) of the axle drive device (10) are combined with a respectively assigned transmission (12) in an electric axle to drive the individually suspended wheels (2) of the axle by means of, in each case, one articulated shaft flange (13) via a respective articulated shaft. Frequency converters assigned respectively to the two electric machines are combined in a converter unit.Type: ApplicationFiled: February 1, 2011Publication date: August 11, 2011Applicant: Dr. Ing. h.c.F. Porsohe AktiengesellschaftInventors: Hartmut Chodura, Guan Chew, Steffen Maurer, Patrik Gisch, Miroslaw Oslislok, Ralf Bauer, Stefan Bobbo
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Publication number: 20110193161Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.Type: ApplicationFiled: February 8, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Zhu, Lee-Wee Teo, Han-Guan Chew, Harry Hak-Lay Chuang
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Publication number: 20110108928Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance.Type: ApplicationFiled: November 12, 2009Publication date: May 12, 2011Applicant: TAIWAN SEMCONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lee-Wee Tao, Han-Guan Chew, Harry Hak-Lay Chuang, Syun-Ming Jang