Abstract: The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter.

Abstract: An analog-to-digital converter includes an input configuration module, an analog-to-digital conversion module, an adaptive parameter extraction module, and a full-period data restoration module. In a parameter extraction working mode, correction parameters are extracted through cooperation of the input configuration module, the analog-to-digital conversion module, the adaptive parameter extraction module, and the full-period data restoration module. In a normal working mode, digital calibration and correction of digital signals are implemented by using the analog-to-digital conversion module and the correction parameters. The correction parameters include a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter.

Abstract: A low-jitter random clock generation circuit includes: a clock division and pulse generation module connected to an input clock, performing frequency division processing to obtain frequency division clocks, and then detecting some frequency division clocks one by one to obtain frequency division pulses in a one-to-one correspondence; a pseudorandom number generation module connected to one frequency division clock, and generating a pseudorandom number; a status control module connected to all the frequency division clocks and the pseudorandom number to generate status control signals; and a random clock output module connected to the input clock, all the frequency division clocks, all the frequency division pulses, and all the status control signals, randomly sampling the frequency division clocks by using the frequency division pulses under control of the status control signals, and synchronously outputting the randomly sampled frequency division clocks by using the input clock, to obtain random clocks.

Abstract: In a pipelined analog-to-digital converter, at least one pipeline stage includes an N-bit sub-analog-to-digital conversion module, a first sub-digital-to-analog conversion module, a second sub-digital-to-analog conversion module, and a switched capacitor amplification module. The first sub-digital-to-analog conversion module and the second sub-digital-to-analog conversion module respectively receive and process 2N?1 digital signals, which correspondingly require 2*2N?1 switched capacitors. In a pipeline stage based on a structure of “N-bit sub-analog-to-digital conversion module+sub-digital-to-analog conversion module+subtractor+multiplier”, the non-inverting input and the inverting input of the differential input comparison are completely symmetrical, which correspondingly requires 2*2N switched capacitors.

Abstract: The comparator includes an input unit, a load unit, a control switch, and an adjustment unit. The input ends of the input unit are connected to a first input signal and a second input signal. The load unit is connected to the input unit, and the gain of the comparator is adjusted by changing the gate voltages of the pair of gain adjustment transistors of the load unit. The adjustment unit is connected to the input unit, and the gate voltages of the pair of gain adjustment transistors are adjusted according to the enable state of the control switch. The present disclosure also provides an analog-to-digital converter.

Abstract: A comparison method includes: providing a successive approximation register analog-to-digital converter, where the successive approximation register analog-to-digital converter includes n?1 weighted capacitors, a charge transfer capacitor, and a comparator; sampling an differential input signal by using the first weighted capacitor and the charge transfer capacitor; importing the differential input signal stored on the charge transfer capacitor, where the differential input signal is transferred and redistributed on the charge transfer capacitor and n?2 other weighted capacitors than the first weighted capacitor, and completing the first time of comparison; and importing the differential input signal stored on the first weighted capacitor and the differential input signal stored on the charge transfer capacitor, importing a reference voltage by using the second to jth weighted capacitors, where the differential input signal and the reference voltage are transferred and redistributed on a capacitor array, and

Abstract: A method for correcting an analog-to-digital converter includes the following steps: extracting gain errors and weight errors of all conversion stages of an analog-to-digital converter; performing first correction on the analog-to-digital converter based on the gain errors and the weight errors; extracting jitter errors of all conversion stages of the analog-to-digital converter after the first correction; and performing a second correction on the analog-to-digital converter based on the jitter errors. According to the disclosure, the gain errors, the weight errors, and the jitter errors of all conversion stages are successively extracted, and then the analog-to-digital converter is corrected. Precision after the corrections is higher.

Abstract: An adaptive current generation circuit includes an inverter drive chain, a frequency divider, a frequency detector, a low-pass filter, a static comparator group, and a controllable current mirror. An input analog signal of the input buffer is converted into a frequency discrimination voltage in a direct current form sequentially through conversion of the inverter drive chain, frequency division of the frequency divider, frequency detection of the frequency detector, and conversion of the low-pass filter. Then the static comparator group performs a plurality of times of comparison to obtain N bits of digital codes. Finally, the controllable current mirror is controlled by using the N bits of digital codes. The controllable current mirror provides a magnitude-adjustable input current for the input buffer under control of the N bits of digital codes. A magnitude of the input current is positively correlated with a frequency of the input analog signal.

Abstract: A comparator based on a pre-amplifier stage structure and an analog-to-digital converter are provided. The comparator includes: a first pre-amplifier stage, where an input terminal of the first pre-amplifier stage is connected to a differential input signal, to amplify and output the differential input signal so as to output a first differential output signal; a second pre-amplifier stage, where an input terminal of the second pre-amplifier stage is connected to the first differential output signal, to amplify and output the first differential output signal so as to output a second differential output signal, and a positive feedback unit is disposed between an output terminal of the second pre-amplifier stage and the input terminal of the second pre-amplifier stage, to increase a voltage gain of the second pre-amplifier stage by using the positive feedback unit; and a latch, an input terminal thereof connected to the second differential output signal.

Abstract: A digital temperature sensor circuit is disclosed. The digital temperature sensor circuit includes a proportional to the absolute temperature (PTAT) current source, generating a PTAT current proportional to absolute temperature; a sigma-delta modulation module, including an integrator, an analog-to-digital conversion unit, and a feedback digital-to-analog conversion unit; the integrator converts the PTAT current into temperature voltage; the analog-to-digital conversion unit compares the temperature voltage with a band gap reference voltage to generate a digital modulation signal with a duty ratio proportional to the temperature; the feedback digital-to-analog conversion unit adjusts the voltage input by the analog-to-digital conversion unit and controls the charging and discharging speed of the integrator; a digital filter, quantizing the digital modulation signal into a digital signal, and outputting the digital signal.

Abstract: Reference voltage circuits and methods for designing the same are provided. The reference voltage circuit includes: a reference core unit configured to output a reference voltage; a main amplification unit connected to the reference core unit and configured to form feedback to the reference core unit; and a feedforward amplification unit connected to the main amplification unit and configured to form feedforward to the main amplification unit. The reference core unit, the main amplification unit, and the feedforward amplification unit form a third-order negative feedback loop to improve a power supply rejection ratio of the reference voltage.

Abstract: A method for calibrating an analog-to-digital converter includes the following steps: conducting an initial performance test and judgement on the analog-to-digital converter; if the initial performance test succeeds, performing a pre-trimming and judgement on the analog-to-digital converter; if the pre-trimming succeeds, performing an error extraction on the analog-to-digital converter, obtaining errors of conversion stages of the analog-to-digital converter; performing an error soft trimming and test on the analog-to-digital converter according to the errors of the conversion stages; and if the error soft trimming and test of the analog-to-digital converter succeed, performing an error hard trimming and test on the analog-to-digital converter according to the errors of the conversion stages.

Abstract: A circuit for channel randomization based on time-interleaved ADC includes: a channel selection module for outputting M clock reception control signals and encoded N data reception control signals based on a main clock and a generated random number; a multi-phase clock distribution module for generating N multi-phase clocks according to a sampling main clock, redistributing the multi-phase clocks according to the clock reception control signals, and outputting M redistributed clock signals; a time-interleaved ADC module for outputting M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signals; an adjustable delay module for setting a delay length for the data reception control signals; and a timing distribution control module for controlling, according to delayed data reception control signals and the channel quantization completion signals, the output data to be output sequentially in chronological order.

Abstract: A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.

Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Abstract: The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter.

Abstract: A resin composition, and a resin film, a prepreg, a laminated board, a copper-clad board, and a printed circuit board which comprise same. The resin composition comprises a combination of thermosetting polyphenylene ether resin, vinyl organic silicon resin, and a fully hydrogenated elastomeric polymer; and based on 100 parts by weight of the sum of the addition amounts of the thermosetting polyphenylene ether resin, the vinyl organic silicon resin, and the fully hydrogenated elastomeric polymer, the addition amount of the fully hydrogenated elastomer polymer is 20-50 parts by weight. The copper-clad board prepared from the resin composition has the characteristics of low dielectric constant, low dielectric loss, excellent thermal-oxidative aging resistance, high glass transition temperature, high heat resistance, high peel strength, low water absorption rate, and the like, and can be applied to scenes such as automobile radars in worse use environments.

Abstract: The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.

Abstract: A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.