Abstract: A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.

Abstract: The present invention provides a frequency-compensated transconductance amplifier, includes an input stage consisting of NMOS transistors M1 and M2, a first-stage active load consisting of PMOS transistors M3 and M4, a first-stage tail current source consisting of a constant current source Iss, a second-stage input transistor consisting of a PMOS transistor M5, a second-stage constant current source consisting of an NMOS transistor M6, a load capacitor consisting of a capacitor CL, and a frequency compensation network formed by sequentially connecting a gain stage GAIN, a compensating resistor Rc and a compensating capacitor Cc in series.

Abstract: Provided are a polyphenyl ether resin composition and a prepreg and a laminated board containing same. The polyphenyl ether resin composition comprises the following components: (1) a tetrafunctional or higher multifunctional acrylate-modified thermosetting polyphenyl ether resin; and (2) a vinyl eresin cross-linking agent, the weight of the vinyl resin cross-linking agent being 40-100 parts by weight based on 100 parts by weight of the tetrafunctional or higher multifunctional acrylate-modified thermosetting polyphenyl ether resin. The modified thermosetting polyphenyl ether resin, due to containing a tetrafunctional or higher multifunctional acrylate active group, can cross-link more vinyl resin cross-linking agents.

Abstract: A method for an analog-to-digital converter correcting error estimation includes: according to a correction parameter preset initial value, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to a correction parameter initial value, correcting a gain error between channels, generating and buffering a general correction signal, and triggering a counting cell to start counting, and calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting to a preset value, setting low-pass filter accumulating cell enable ends and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching it, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching them, and resetting to carry out cyclic estimat

Abstract: Disclosed in the present invention is a resin composition, comprising a modified polyphenylene ether resin and an organic silicon compound containing unsaturated double bonds. Also disclosed is a method for preparing a high-frequency circuit substrate using the resin composition as described above and a high-frequency circuit substrate obtained by the preparation method. The high-frequency circuit substrate of the present invention has a high glass transition temperature, a high thermal decomposition temperature, a high interlayer adhesive force, a low dielectric constant and a low dielectric loss tangent, and is very suitable as a circuit substrate in a high-frequency electronic device.

Abstract: An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.

Abstract: The present invention relates to a polyphenyl ether resin composition and a use thereof in a high-frequency circuit substrate. The polyphenyl ether resin composition comprises a vinyl-modified polyphenyl ether resin and an organic silicon resin containing unsaturated double bonds and having a three-dimensional net structure. The high-frequency circuit substrate of the present invention has the advantages of a low dielectric constant, a low dielectric loss, high heat resistance, low water absorption, a high interlayer adhesive force and a high bending strength, and is very suitable as a circuit substrate of high-speed electronic equipment.

Abstract: The present invention relates to a polyphenyl ether resin composition and a use thereof in a high-frequency circuit substrate. The polyphenyl ether resin composition comprises a vinyl-modified polyphenyl ether resin and an organic silicon resin containing unsaturated double bonds and having a three-dimensional net structure. The high-frequency circuit substrate of the present invention has a high glass-transition temperature, a high thermal decomposition temperature, a high interlayer adhesive force, a low dielectric constant and a low dielectric loss tangent, and is very suitable as a circuit substrate of high-speed electronic equipment.

Abstract: The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.

Abstract: The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.

Abstract: The present invention provides a frequency-compensated transconductance amplifier, includes an input stage consisting of NMOS transistors M1 and M2, a first-stage active load consisting of PMOS transistors M3 and M4, a first-stage tail current source consisting of a constant current source Iss, a second-stage input transistor consisting of a PMOS transistor M5, a second-stage constant current source consisting of an NMOS transistor M6, a load capacitor consisting of a capacitor CL, and a frequency compensation network formed by sequentially connecting a gain stage GAIN, a compensating resistor Rc and a compensating capacitor Cc in series.

Abstract: Provided in the present invention are a resin composition and a pre-preg and a laminate using the composition. The resin composition comprises: (A) a prepolymer of a polyolefin resin and a bifunctional maleimide or a multifunctional maleimide; and, (B) vinyl thermosetting polyphenylene ether, where with the weight of the prepolymer of the polyolefin resin and the bifunctional maleimide or the multifunctional maleimide being 100 parts by weight, the weight of the vinyl thermosetting polyphenylene ether is 200 to 1000 parts by weight. The present invention, by employing the prepolymer of the polyolefin resin and the bifunctional maleimide or the multifunctional maleimide, solves the problem of incompatibility of the bifunctional maleimide or the multifunctional maleimide with the polyolefin resin and vinyl thermosetting polyphenylene ether. An aqueous glue solution so mixed is uniform and consistent, the pre-preg has a uniform expression, and a substrate resin area is free of a phase-separation problem.

Abstract: An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.

Abstract: The present invention relates to the technical field of copper clad laminates and relates to a resin composition and a pre-preg and a laminate using the composition. The resin composition comprises: (A) a prepolymer of vinyl thermosetting polyphenylene ether and a bifunctional maleimide or a multifunctional maleimide; and, (B) a polyolefin resin. The present invention, by employing the prepolymer of vinyl thermosetting polyphenylene ether and the bifunctional maleimide or the multifunctional maleimide, solves the problem of incompatibility of the bifunctional maleimide or the multifunctional maleimide with the vinyl thermosetting polyphenylene ether and the polyolefin resin. An aqueous glue solution so mixed is uniform and consistent, the prepreg has a uniform expression, and a substrate resin area is free of a phase-separation problem.

Abstract: The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof.

Abstract: A high-speed sampling front-end circuit is presented that includes a MDAC sampling network, a reference voltage generator circuit, a comparator array, an operational amplifier, an output short-circuit switch, an adjustable clock duty cycle stabilizer, a status control module and a feedback control module. The circuit features low power, high sampling rate and high input bandwidth of sampling network. The time constant of the MDAC sampling network and the comparator array is precisely matched one another to improve input bandwidth of the sampling network. Sampling capacitors are designed as feedback capacitors and DAC calculation capacitors, thereby the operational amplifier doubles feedback coefficient and features 50% bandwidth and 50% power. The cycle stabilizer is adopted to shorten sampling time and extend amplification phase to greatly improve sampling rate. One input reference voltage tends to simplify the design of the reference voltage generator circuit.

Abstract: The present invention discloses a resin composition, comprising an unsaturated thermosetting modified polyphenylether resin and an MQ organosilicon resin containing unsaturated double bonds and having a three-dimensional network structure and hydrolytically condensed from monofunctional siloxane unit (M unit) and tetrafunctional silica unit (Q unit). The present invention further discloses a high-frequency circuit substrate prepared from the aforesaid resin composition and the uses of the aforesaid resin composition in the art. The high frequency circuit substrate of the present invention has a high glass transition temperature, a high thermal decomposition temperature, a high interstratified adhesive force, a low dielectric constant and a low dielectric loss tangent, and are very suitable as the circuit substrates of high frequency electronic equipments.

Abstract: Disclosed in the present invention is a resin composition, comprising a modified polyphenylene ether resin and an organic silicon compound containing unsaturated double bonds. Also disclosed is a method for preparing a high-frequency circuit substrate using the resin composition as described above and a high-frequency circuit substrate obtained by the preparation method. The high-frequency circuit substrate of the present invention has a high glass transition temperature, a high thermal decomposition temperature, a high interlayer adhesive force, a low dielectric constant and a low dielectric loss tangent, and is very suitable as a circuit substrate in a high-frequency electronic device.

Abstract: The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

Abstract: A high-speed sampling front-end circuit is presented that includes a MDAC sampling network, a reference voltage generator circuit, a comparator array, an operational amplifier, an output short-circuit switch, an adjustable clock duty cycle stabilizer, a status control module and a feedback control module. The circuit features low power, high sampling rate and high input bandwidth of sampling network. The time constant of the MDAC sampling network and the comparator array is precisely matched one another to improve input bandwidth of the sampling network. Sampling capacitors are designed as feedback capacitors and DAC calculation capacitors, thereby the operational amplifier doubles feedback coefficient and features 50% bandwidth and 50% power. The cycle stabilizer is adopted to shorten sampling time and extend amplification phase to greatly improve sampling rate. One input reference voltage tends to simplify the design of the reference voltage generator circuit.